STM32L4R5 — ADC Configuration (DMA, Oversampling)
Register-level and HAL configuration of the STM32L4R5 12-bit SAR ADCs — clock & calibration, channel sequencing, sampling time, hardware oversampling to 16-bit, and circular DMA for multi-channel acquisition.
STM32L4R5 — DMA & DMAMUX Request Routing
Two 7-channel DMA controllers plus the DMAMUX1 request router — CCR/CNDTR/CPAR/CMAR, mem2periph & periph2mem, circular streaming, the full request-line table, and complete ADC+DMA and UART+DMA examples for the STM32L4R5 (RM0432).
STM32L4R5 — GPIO & Alternate-Function Pin Mux
Register-accurate reference for MODER/OTYPER/OSPEEDR/PUPDR/IDR/ODR/BSRR/AFRL/AFRH on the STM32L4R5 (Cortex-M4F, RM0432) — with LL and HAL variants, AF maps, and fast BSRR toggling.
STM32L4R5 — I2C (TIMINGR, Master TX/RX)
The STM32L4R5 uses the "I2Cv2" peripheral: no more CCR/TRISE — one TIMINGR register sets the whole bus timing, and CR2 (NBYTES + AUTOEND + START) drives fully hardware-sequenced master reads and writes. Register-level and HAL code for I2C1–I2C4.
STM32L4R5 — NVIC, EXTI & Interrupt Handling
The full external-interrupt signal chain — GPIO edge to SYSCFG mux to EXTI to NVIC to your ISR — with exact RM0432 register names, CMSIS macros, a compilable bare-metal button example and the HAL equivalent.
STM32L4R5 — Low-Power Modes & Wakeup
Run, Sleep, Stop 0/1/2, Standby and Shutdown on the STM32L4R5 (Cortex-M4F, RM0432): the PWR CR1–CR4 / SR / SCR registers, the SLEEPDEEP + WFI/WFE mechanism, RAM retention, wakeup sources and a complete RTC periodic-wakeup example.
STM32L4R5 — Chip Overview & Memory Map
Cortex-M4F at 120 MHz, 2 MB dual-bank flash and 640 KB SRAM — the address map, bus matrix, peripheral set, packages, boot modes and option bytes you need before writing a single register.
STM32L4R5 — RCC Clock Tree & 120 MHz Setup
Register-level clock bring-up for the STM32L4R5 (Cortex-M4F, RM0432): PWR Range 1 boost, flash wait states, PLL math and a complete, compilable 120 MHz init.
STM32L4R5 — SPI Master (CPOL/CPHA, DMA)
Register-level and HAL configuration of SPI1/2/3 in master mode on the STM32L4R5 (Cortex-M4F, RM0432): CR1/CR2 bit fields, the four clock modes, baud prescaler, NSS management, 8/16-bit framing, the RX/TX FIFO and full-duplex DMA over DMAMUX1.
STM32L4R5 — Timers (PWM, Input Capture, Encoder)
Register-accurate map of every TIMx and LPTIMx on the STM32L4R5 (RM0432 / DS12023): time-base math, PWM edge/center, complementary outputs with dead-time, input capture, quadrature encoder and one-pulse — with copy-pasteable bare-metal and HAL code.
STM32L4R5 — USART / LPUART (Poll, IRQ, DMA)
Register-accurate serial for the STM32L4R5 (Cortex-M4F, RM0432): USART1-3, UART4-5 and LPUART1 — BRR baud math with oversampling 16/8, the CR1/CR2/CR3 bit fields, TXE/RXNE/TC flags, and complete polling, interrupt and DMAMUX-driven code in both bare-metal and HAL form.