GPIO Pin Mux
Alternate Functions on the STM32L4R5

typedef struct {
    volatile uint32_t MODER;    /* 0x00  mode        (2 bits/pin) */
    volatile uint32_t OTYPER;   /* 0x04  output type (1 bit/pin)  */
    volatile uint32_t OSPEEDR;  /* 0x08  speed       (2 bits/pin) */
    volatile uint32_t PUPDR;    /* 0x0C  pull up/dn  (2 bits/pin) */
    volatile uint32_t IDR;      /* 0x10  input data  (read-only)  */
    volatile uint32_t ODR;      /* 0x14  output data              */
    volatile uint32_t BSRR;     /* 0x18  bit set/reset (atomic)   */
    volatile uint32_t LCKR;     /* 0x1C  config lock              */
    volatile uint32_t AFR[2];   /* 0x20 AFRL (0-7), 0x24 AFRH (8-15) */
    volatile uint32_t BRR;      /* 0x28  bit reset                */
    /* NOTE: no ASCR on L4R5 (L4+) — struct ends here */
} GPIO_TypeDef;

/* 2-bit fields (MODER / OSPEEDR / PUPDR): shift = 2*n, mask = 0x3 */
#define MODE_MASK(n)   (0x3UL << ((n) * 2))
#define MODE_VAL(n,v)  (((uint32_t)(v)) << ((n) * 2))

/* 1-bit fields (OTYPER / IDR / ODR): shift = n */
#define BIT(n)         (1UL << (n))

/* BSRR: set pin n -> bit n ; reset pin n -> bit n+16 */
#define BSRR_SET(n)    (1UL << (n))
#define BSRR_RST(n)    (1UL << ((n) + 16))

/* AFR nibble: pins 0-7 use AFR[0], pins 8-15 use AFR[1] */
#define AFR_IDX(n)     ((n) >> 3)          /* 0 or 1            */
#define AFR_SH(n)      (((n) & 7) * 4)      /* nibble position  */
#define AFR_MASK(n)    (0xFUL << AFR_SH(n))
#define AFR_VAL(n,af)  (((uint32_t)(af)) << AFR_SH(n))

RCC->AHB2ENR |= (1UL << 2);          /* GPIOCEN */
(void)RCC->AHB2ENR;                   /* sync read after clock enable */

GPIOC->MODER &= ~(0x3UL << (13*2));   /* 00 = input */
GPIOC->PUPDR &= ~(0x3UL << (13*2));
GPIOC->PUPDR |=  (0x1UL << (13*2));   /* 01 = pull-up */

int pressed = (GPIOC->IDR & (1UL << 13)) == 0;  /* B1 is active-low */

RCC->AHB2ENR |= (1UL << 1);           /* GPIOBEN */
(void)RCC->AHB2ENR;

GPIOB->MODER   &= ~(0x3UL << (7*2));
GPIOB->MODER   |=  (0x1UL << (7*2));  /* 01 = output */
GPIOB->OTYPER  &= ~(1UL   << 7);      /* 0  = push-pull */
GPIOB->OSPEEDR &= ~(0x3UL << (7*2)); /* 00 = low speed (LED needs nothing more) */
GPIOB->PUPDR   &= ~(0x3UL << (7*2)); /* no pull */

GPIOB->BSRR = (1UL << 7);             /* drive high */

RCC->AHB2ENR |= (1UL << 0);           /* GPIOAEN */
(void)RCC->AHB2ENR;

GPIOA->MODER   &= ~(0x3UL << (5*2));
GPIOA->MODER   |=  (0x2UL << (5*2));  /* 10 = alternate function */
GPIOA->OTYPER  &= ~(1UL   << 5);      /* push-pull (SPI clock) */
GPIOA->OSPEEDR |=  (0x3UL << (5*2)); /* 11 = very-high for clean SPI edges */

/* AF5 into AFRL nibble for pin 5 (pins 0-7 -> AFR[0]) */
GPIOA->AFR[0] &= ~(0xFUL << (5*4));
GPIOA->AFR[0] |=  (5UL   << (5*4));   /* 5 = AF5 = SPI1 */

RCC->AHB2ENR |= (1UL << 0);           /* GPIOAEN */
(void)RCC->AHB2ENR;

GPIOA->MODER |= (0x3UL << (0*2));     /* 11 = analog. That is all — */
                                     /* the L4R5 has no ASCR to set. */
GPIOA->PUPDR &= ~(0x3UL << (0*2));    /* disable pulls on an analog pin */

#include <stdint.h>

/* ---- minimal register model (RM0432 addresses) ---- */
typedef struct {
    volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR;
    volatile uint32_t IDR, ODR, BSRR, LCKR;
    volatile uint32_t AFR[2];        /* AFRL @0x20, AFRH @0x24 */
    volatile uint32_t BRR;           /* @0x28  (no ASCR on L4R5) */
} GPIO_TypeDef;

typedef struct {
    volatile uint32_t CR1, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ICR, RDR, TDR;
} USART_TypeDef;

#define GPIOA   ((GPIO_TypeDef *)0x48000000UL)
#define GPIOB   ((GPIO_TypeDef *)0x48000400UL)
#define USART2  ((USART_TypeDef *)0x40004400UL)

#define RCC_AHB2ENR   (*(volatile uint32_t *)0x4002104CUL)
#define RCC_APB1ENR1  (*(volatile uint32_t *)0x40021058UL)

#define GPIOAEN   (1UL << 0)
#define GPIOBEN   (1UL << 1)
#define USART2EN  (1UL << 17)          /* RCC_APB1ENR1 bit 17 */

#define USART_CR1_UE  (1UL << 0)
#define USART_CR1_RE  (1UL << 2)
#define USART_CR1_TE  (1UL << 3)
#define USART_ISR_TXE (1UL << 7)

#define LED_PIN   7                    /* PB7 = blue LED (LD2) */

static void delay(volatile uint32_t n) { while (n--) __asm__ volatile("nop"); }

static void led_init(void)
{
    RCC_AHB2ENR |= GPIOBEN;
    (void)RCC_AHB2ENR;                 /* sync after clock enable */

    GPIOB->MODER   &= ~(0x3UL << (LED_PIN * 2));
    GPIOB->MODER   |=  (0x1UL << (LED_PIN * 2));   /* output */
    GPIOB->OTYPER  &= ~(1UL   << LED_PIN);         /* push-pull */
    GPIOB->OSPEEDR &= ~(0x3UL << (LED_PIN * 2));   /* low speed */
    GPIOB->PUPDR   &= ~(0x3UL << (LED_PIN * 2));   /* no pull */
}

static void usart2_init(void)
{
    RCC_AHB2ENR  |= GPIOAEN;
    RCC_APB1ENR1 |= USART2EN;
    (void)RCC_APB1ENR1;

    /* PA2 (TX) and PA3 (RX) -> AF mode */
    GPIOA->MODER &= ~((0x3UL << (2*2)) | (0x3UL << (3*2)));
    GPIOA->MODER |=  ((0x2UL << (2*2)) | (0x2UL << (3*2)));   /* 10 = AF */

    /* AF7 for pins 2 and 3, both in AFRL (AFR[0]) */
    GPIOA->AFR[0] &= ~((0xFUL << (2*4)) | (0xFUL << (3*4)));
    GPIOA->AFR[0] |=  ((7UL   << (2*4)) | (7UL   << (3*4)));

    /* 9600 8N1, PCLK1 = 4 MHz (MSI reset default), OVER8=0 */
    USART2->BRR = 4000000UL / 9600UL;              /* ~416 */
    USART2->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE;
}

static void usart2_putc(char c)
{
    while (!(USART2->ISR & USART_ISR_TXE)) { }
    USART2->TDR = (uint8_t)c;
}

int main(void)
{
    led_init();
    usart2_init();

    for (;;) {
        GPIOB->BSRR = (1UL << LED_PIN);            /* LED on  (atomic) */
        usart2_putc('*');
        delay(400000);
        GPIOB->BSRR = (1UL << (LED_PIN + 16));     /* LED off (atomic) */
        delay(400000);
    }
}

/* Atomic, ISR-safe — preferred */
GPIOB->BSRR = (1UL << 7);          /* PB7 = 1  (lower half = SET)   */
GPIOB->BSRR = (1UL << (7 + 16));   /* PB7 = 0  (upper half = RESET) */
GPIOB->BRR  = (1UL << 7);          /* PB7 = 0  (BRR is reset-only)  */

/* Set several pins, clear others, in ONE write: */
GPIOB->BSRR = (1UL << 0) | (1UL << 1) | (1UL << (2 + 16));
/* -> PB0=1, PB1=1, PB2=0 simultaneously */

/* Software toggle needs a read of ODR — NOT atomic vs. an ISR
   touching another pin on the same port: */
GPIOB->ODR ^= (1UL << 7);

/* Maximum square-wave: back-to-back BSRR stores.
   GPIO is on AHB2, so the rate is limited by store latency at HCLK. */
for (;;) {
    GPIOB->BSRR = (1UL << 7);
    GPIOB->BSRR = (1UL << (7 + 16));
}

#include "stm32l4xx_ll_bus.h"
#include "stm32l4xx_ll_gpio.h"

LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);

LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_7, LL_GPIO_MODE_OUTPUT);
LL_GPIO_SetPinOutputType(GPIOB, LL_GPIO_PIN_7, LL_GPIO_OUTPUT_PUSHPULL);
LL_GPIO_SetPinSpeed(GPIOB, LL_GPIO_PIN_7, LL_GPIO_SPEED_FREQ_LOW);
LL_GPIO_SetPinPull(GPIOB, LL_GPIO_PIN_7, LL_GPIO_PULL_NO);

LL_GPIO_SetOutputPin(GPIOB, LL_GPIO_PIN_7);     /* -> BSRR set   */
LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);   /* -> BRR / BSRR */
LL_GPIO_TogglePin(GPIOB, LL_GPIO_PIN_7);        /* reads ODR, writes BSRR */

/* AF pin: PA2 = USART2_TX (AF7). AFRL helper for pins 0-7: */
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_2, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_2, LL_GPIO_AF_7);
/* pins 8-15 would use LL_GPIO_SetAFPin_8_15() for AFRH */

#include "stm32l4xx_hal.h"

__HAL_RCC_GPIOB_CLK_ENABLE();

GPIO_InitTypeDef led = {0};
led.Pin   = GPIO_PIN_7;
led.Mode  = GPIO_MODE_OUTPUT_PP;
led.Pull  = GPIO_NOPULL;
led.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &led);

HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET);   /* uses BSRR */
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7);

/* Alternate function: USART2 TX/RX on PA2/PA3 */
__HAL_RCC_GPIOA_CLK_ENABLE();
GPIO_InitTypeDef af = {0};
af.Pin       = GPIO_PIN_2 | GPIO_PIN_3;
af.Mode      = GPIO_MODE_AF_PP;
af.Pull      = GPIO_PULLUP;
af.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
af.Alternate = GPIO_AF7_USART2;        /* the AF7 nibble, chosen by macro */
HAL_GPIO_Init(GPIOA, &af);