STM32L4R5 ADC
DMA, Oversampling & Calibration

/* All symbols below ship in the CubeL4 CMSIS device header. */
#include <stdint.h>
#include "stm32l4r5xx.h"

ADC_TypeDef        *a1 = ADC1;          // 0x50040000
ADC_TypeDef        *a2 = ADC2;          // 0x50040100
ADC_Common_TypeDef *ac = ADC12_COMMON;  // 0x50040300 (shared CCR)

/* Crude blocking microsecond delay (replace with a timer/DWT in real code). */
static void delay_us(volatile uint32_t n){ while(n--) { for(volatile int i=0;i<20;i++){} } }

void adc1_init_clock_and_calibrate(void)
{
    /* 1. ADC peripheral (bus) clock on AHB2 */
    RCC->AHB2ENR |= RCC_AHB2ENR_ADCEN;
    (void)RCC->AHB2ENR;                 // dummy read: RCC clock-enable settling

    /* 2. Async kernel clock = SYSCLK, common prescaler /4 */
    RCC->CCIPR |= (3U << RCC_CCIPR_ADCSEL_Pos);       // 11 = SYSCLK
    ADC12_COMMON->CCR &= ~ADC_CCR_CKMODE;             // 00 = asynchronous
    ADC12_COMMON->CCR &= ~ADC_CCR_PRESC;
    ADC12_COMMON->CCR |= (0x2U << ADC_CCR_PRESC_Pos);  // 0010 = /4

    /* 3-4. Exit deep-power-down, enable regulator, wait start-up */
    ADC1->CR &= ~ADC_CR_DEEPPWD;
    ADC1->CR |= ADC_CR_ADVREGEN;
    delay_us(20);                                     // t_ADCVREG_STUP

    /* 5. Single-ended calibration (ADEN must be 0 here) */
    ADC1->CR &= ~ADC_CR_ADCALDIF;                     // single-ended factor
    ADC1->CR |= ADC_CR_ADCAL;
    while (ADC1->CR & ADC_CR_ADCAL) { }                 // cleared by HW when done
    // calibration factor is now in ADC1->CALFACT

    /* 6. Enable the ADC and wait until it is ready */
    ADC1->ISR = ADC_ISR_ADRDY;                        // clear (write-1-to-clear)
    ADC1->CR |= ADC_CR_ADEN;
    while (!(ADC1->ISR & ADC_ISR_ADRDY)) { }
    ADC1->ISR = ADC_ISR_ADRDY;
}

uint16_t adc1_read_pa0(void)
{
    /* PA0 analog + close the analog switch (ASCR) */
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
    GPIOA->MODER |= (3U << (0 * 2));       // PA0 = analog (11)
    GPIOA->PUPDR &= ~(3U << (0 * 2));      // no pull
    GPIOA->ASCR  |= GPIO_ASCR_ASC0;        // route analog signal to ADC

    ADC1->CFGR &= ~ADC_CFGR_RES;           // 12-bit (RES = 00)

    /* channel 5 sampling = 47.5 cycles (SMP5 = 100) */
    ADC1->SMPR1 &= ~(0x7U << ADC_SMPR1_SMP5_Pos);
    ADC1->SMPR1 |=  (0x4U << ADC_SMPR1_SMP5_Pos);

    /* sequence: 1 conversion, SQ1 = channel 5 */
    ADC1->SQR1 &= ~ADC_SQR1_L;             // L = 0 -> one conversion
    ADC1->SQR1 &= ~ADC_SQR1_SQ1;
    ADC1->SQR1 |= (5U << ADC_SQR1_SQ1_Pos);

    ADC1->CFGR &= ~ADC_CFGR_CONT;          // single conversion
    ADC1->CFGR &= ~ADC_CFGR_EXTEN;         // software trigger

    ADC1->CR |= ADC_CR_ADSTART;
    while (!(ADC1->ISR & ADC_ISR_EOC)) { }
    return (uint16_t)ADC1->DR;              // reading DR clears EOC
}

/* Factory calibration values in system memory (STM32L4 addresses). */
#define VREFINT_CAL   (*(uint16_t*)0x1FFF75AAUL)   // @3.0V, 30C
#define TS_CAL1       (*(uint16_t*)0x1FFF75A8UL)   // 30C
#define TS_CAL2       (*(uint16_t*)0x1FFF75CAUL)   // 130C

void adc1_enable_internal_paths(void)
{
    ADC12_COMMON->CCR |= ADC_CCR_VREFEN;    // VREFINT  (ch 0)
    ADC12_COMMON->CCR |= ADC_CCR_CH17SEL;   // temp     (ch 17)
    ADC12_COMMON->CCR |= ADC_CCR_CH18SEL;   // VBAT/3   (ch 18)
    // Use SMP = 111 (640.5 cyc) for these channels; the temp sensor
    // also needs its start-up time (~tens of µs) after CH17SEL = 1.
}

/* vref_data / ts_data = raw 12-bit conversions of ch0 / ch17 */
float vdda_millivolts(uint16_t vref_data)
{
    return 3000.0f * (float)VREFINT_CAL / (float)vref_data;
}

float temperature_celsius(uint16_t ts_data, float vdda_mv)
{
    /* rescale the live reading to the 3.0 V calibration reference */
    float ts = (float)ts_data * vdda_mv / 3000.0f;
    return (130.0f - 30.0f) / (float)(TS_CAL2 - TS_CAL1)
         * (ts - (float)TS_CAL1) + 30.0f;
}

void adc1_enable_16bit_oversampling(void)
{
    ADC1->CFGR2 &= ~(ADC_CFGR2_OVSR | ADC_CFGR2_OVSS);
    ADC1->CFGR2 |= (0x7U << ADC_CFGR2_OVSR_Pos);   // 111 = 256x ratio
    ADC1->CFGR2 |= (0x4U << ADC_CFGR2_OVSS_Pos);   // shift right by 4 bits
    ADC1->CFGR2 |= ADC_CFGR2_ROVSE;               // enable regular oversampling
    // One ADSTART now yields ONE 16-bit oversampled sample in DR.
    // Configure CFGR2 while the ADC is enabled but NOT converting.
}

#define NCH 3
static volatile uint16_t adc_buf[NCH];   // DMA target (half-words)

/* Assumes adc1_init_clock_and_calibrate() ran and ADC1 is DISABLED. */
void adc1_start_scan_dma(void)
{
    /* sequence: ch1, ch2, ch17(temp) -> L = 2 (three conversions) */
    ADC1->SQR1 = (2U  << ADC_SQR1_L_Pos)
               | (1U  << ADC_SQR1_SQ1_Pos)
               | (2U  << ADC_SQR1_SQ2_Pos)
               | (17U << ADC_SQR1_SQ3_Pos);

    /* sampling: 247.5 cyc (110) for all three */
    ADC1->SMPR1 = (6U << ADC_SMPR1_SMP1_Pos) | (6U << ADC_SMPR1_SMP2_Pos);
    ADC1->SMPR2 = (6U << ADC_SMPR2_SMP17_Pos);
    ADC12_COMMON->CCR |= ADC_CCR_CH17SEL;   // enable temp path (ch17)

    /* continuous + DMA + circular + overwrite on overrun */
    ADC1->CFGR |= ADC_CFGR_CONT | ADC_CFGR_DMAEN
                | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD;

    /* ---- DMA1 Channel1 via DMAMUX (request 5 = ADC1) ---- */
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
    DMAMUX1_Channel0->CCR = 5U;                 // DMAREQ_ID = ADC1

    DMA1_Channel1->CCR   = 0;                   // disable while configuring
    DMA1_Channel1->CPAR  = (uint32_t)&ADC1->DR; // source: ADC data reg
    DMA1_Channel1->CMAR  = (uint32_t)adc_buf;   // dest: RAM buffer
    DMA1_Channel1->CNDTR = NCH;
    DMA1_Channel1->CCR   = DMA_CCR_MINC                  // increment memory
                        | (1U << DMA_CCR_PSIZE_Pos)      // 16-bit peripheral
                        | (1U << DMA_CCR_MSIZE_Pos)      // 16-bit memory
                        | DMA_CCR_CIRC                   // circular
                        | DMA_CCR_TCIE;                  // transfer-complete IRQ
    DMA1_Channel1->CCR  |= DMA_CCR_EN;

    /* enable ADC, then start — it now free-runs into adc_buf[] */
    ADC1->ISR = ADC_ISR_ADRDY;
    ADC1->CR |= ADC_CR_ADEN;
    while (!(ADC1->ISR & ADC_ISR_ADRDY)) { }
    ADC1->CR |= ADC_CR_ADSTART;
}

ADC_HandleTypeDef hadc1;
static uint16_t adc_buf[3];

void MX_ADC1_Init(void)
{
    hadc1.Instance                   = ADC1;
    hadc1.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV4;
    hadc1.Init.Resolution            = ADC_RESOLUTION_12B;
    hadc1.Init.ScanConvMode          = ADC_SCAN_ENABLE;
    hadc1.Init.ContinuousConvMode    = ENABLE;
    hadc1.Init.NbrOfConversion       = 3;
    hadc1.Init.DiscontinuousConvMode = DISABLE;
    hadc1.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
    hadc1.Init.DMAContinuousRequests = ENABLE;              // DMACFG = circular
    hadc1.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;

    /* hardware oversampling: 256x, shift 4 -> true 16-bit */
    hadc1.Init.OversamplingMode                = ENABLE;
    hadc1.Init.Oversampling.Ratio              = ADC_OVERSAMPLING_RATIO_256;
    hadc1.Init.Oversampling.RightBitShift      = ADC_RIGHTBITSHIFT_4;
    hadc1.Init.Oversampling.TriggeredMode      = ADC_TRIGGEREDMODE_SINGLE_TRIGGER;
    hadc1.Init.Oversampling.OversamplingStopReset = ADC_REGOVERSAMPLING_CONTINUED_MODE;
    HAL_ADC_Init(&hadc1);

    ADC_ChannelConfTypeDef s = {0};
    s.SingleDiff   = ADC_SINGLE_ENDED;
    s.OffsetNumber = ADC_OFFSET_NONE;
    s.Offset       = 0;

    s.Channel = ADC_CHANNEL_1; s.Rank = ADC_REGULAR_RANK_1;
    s.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
    HAL_ADC_ConfigChannel(&hadc1, &s);

    s.Channel = ADC_CHANNEL_2; s.Rank = ADC_REGULAR_RANK_2;
    HAL_ADC_ConfigChannel(&hadc1, &s);

    s.Channel = ADC_CHANNEL_TEMPSENSOR; s.Rank = ADC_REGULAR_RANK_3;
    s.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;           // internal ch needs long SMP
    HAL_ADC_ConfigChannel(&hadc1, &s);

    /* calibrate (single-ended) then start the circular DMA stream */
    HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
    HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buf, 3);
}