Low-Power Modes
& Wakeup

/* Cortex-M4 System Control Register — CMSIS names */
/* SCB_SCR_SLEEPONEXIT_Msk  (bit 1) : re-sleep on ISR return       */
/* SCB_SCR_SLEEPDEEP_Msk    (bit 2) : 0 = Sleep, 1 = Stop/Standby   */
/* SCB_SCR_SEVONPEND_Msk    (bit 4) : pending IRQ generates an event */

static inline void deepsleep(int on)
{
    if (on) SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
    else    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
    __DSB();          /* ensure the SCR write completes before WFI */
}

#include "stm32l4xx.h"

/* Plain Sleep: SLEEPDEEP=0, so WFI only gates the CPU clock.
   Any NVIC-enabled interrupt wakes and vectors to its handler. */
static void enter_sleep(void)
{
    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;   /* Sleep, not Stop */
    __DSB();
    __WFI();                              /* halt until an interrupt */
}

/* Sleep-on-exit: the core automatically re-sleeps every time it
   returns from an ISR. Perfect for purely event-driven firmware —
   main() sets it once and the while(1) never actually runs. */
static void enable_sleep_on_exit(void)
{
    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
    SCB->SCR |=  SCB_SCR_SLEEPONEXIT_Msk;
    __DSB();
    __WFI();                              /* first sleep; ISRs do the rest */
}

/* Low-power run needs: VOS = Range 2, then SYSCLK <= 2 MHz,
   then set LPR. Order matters. */
static void enter_low_power_run(void)
{
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;

    /* 1. Voltage scaling Range 2 (VOS = 10) */
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_Msk) | (0x2u << PWR_CR1_VOS_Pos);
    while (PWR->SR2 & PWR_SR2_VOSF) { }     /* wait until scaling done */

    /* 2. Drop SYSCLK to <= 2 MHz here (e.g. MSI range 2 MHz) ... */

    /* 3. Enter low-power run */
    PWR->CR1 |= PWR_CR1_LPR;
    while (!(PWR->SR2 & PWR_SR2_REGLPF)) { } /* LPR now supplying core */
}

static void exit_low_power_run(void)
{
    PWR->CR1 &= ~PWR_CR1_LPR;
    while (PWR->SR2 & PWR_SR2_REGLPF) { }    /* back on main regulator */
    /* raise SYSCLK and VOS = Range 1 again as needed */
}

#include "stm32l4xx.h"

/* lpms: 0 = Stop0, 1 = Stop1, 2 = Stop2 */
static void enter_stop(uint32_t lpms)
{
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;

    /* 1. Select the Stop level in LPMS[2:0] */
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS_Msk)
             | (lpms & PWR_CR1_LPMS_Msk);

    /* 2. SLEEPDEEP = 1 so WFI enters Stop, not Sleep */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    /* 3. Barrier, then sleep. Execution resumes HERE on wakeup. */
    __DSB();
    __WFI();

    /* 4. Restore SLEEPDEEP so a later plain Sleep behaves */
    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
}

/* After Stop the tree is MSI-only. Re-arm HSE + PLL and switch back.
   In practice just call your generated SystemClock_Config() again. */
static void restore_clock_after_stop(void)
{
    RCC->CR |= RCC_CR_HSEON;
    while (!(RCC->CR & RCC_CR_HSERDY)) { }

    RCC->CR |= RCC_CR_PLLON;
    while (!(RCC->CR & RCC_CR_PLLRDY)) { }

    RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) { }
}

/* HAL rolls LPMS + SLEEPDEEP + WFI into one call per mode.        */
/* Stop 0 (main regulator kept):                                  */
HAL_PWREx_EnterSTOP0Mode(PWR_STOPENTRY_WFI);

/* Stop 1 (LPR):                                                  */
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);

/* Stop 2 (deepest Stop):                                         */
HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);

/* Every one of these returns on wakeup with the clock on MSI,    */
/* so re-run your clock config immediately:                       */
SystemClock_Config();

#include "stm32l4xx.h"

/* retain_sram2 != 0 keeps the 64-KB SRAM2 alive across Standby
   (powered by the LPR) so you can stash state there. */
static void enter_standby(int retain_sram2)
{
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;

    if (retain_sram2) PWR->CR3 |=  PWR_CR3_RRS;
    else              PWR->CR3 &= ~PWR_CR3_RRS;

    /* LPMS = 011 -> Standby */
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS_Msk)
             | (0x3u << PWR_CR1_LPMS_Pos);

    /* Clear every stale wakeup flag LAST, per RM0432 */
    PWR->SCR = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3
             | PWR_SCR_CWUF4 | PWR_SCR_CWUF5;

    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
    __DSB();
    __WFI();                 /* powers down; wakeup causes a RESET */
}

/* LPMS = 1xx -> Shutdown (use 100). Deepest; ignores RRS. */
static void enter_shutdown(void)
{
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS_Msk)
             | (0x4u << PWR_CR1_LPMS_Pos);
    PWR->SCR = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3
             | PWR_SCR_CWUF4 | PWR_SCR_CWUF5;
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
    __DSB();
    __WFI();
}

/* Arm WKUP1 (PA0) as a rising-edge Standby/Shutdown wakeup. The pad
   itself needs no GPIO clock — the WKUP function is always wired. */
static void configure_wakeup_pin1(void)
{
    PWR->CR4 &= ~PWR_CR4_WP1;    /* WP1 = 0 -> detect a rising edge */
    PWR->SCR  =  PWR_SCR_CWUF1;   /* clear any pending flag first     */
    PWR->CR3 |=  PWR_CR3_EWUP1;   /* enable WKUP1                     */
}

/* At every boot, tell "cold power-on" from "woke from Standby". */
int main(void)
{
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;

    if (PWR->SR1 & PWR_SR1_SBF) {         /* came out of Standby/Shutdown */
        PWR->SCR = PWR_SCR_CSBF;          /* clear the Standby flag       */
        /* SRAM2 is valid only if RRS was set; SRAM1/SRAM3 are cleared.
           Backup registers RTC->BKP0R..BKP31R are always valid.        */
    } else {
        /* genuine cold start: full init */
    }

    configure_wakeup_pin1();
    /* ... */
    for (;;) { }
}

#include "stm32l4xx.h"

/* Enable the LSE and route it to the RTC. Do this once at startup. */
static void rtc_lse_init(void)
{
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;   /* PWR clock             */
    PWR->CR1 |= PWR_CR1_DBP;                /* unlock backup domain  */

    /* Start the 32.768 kHz LSE crystal */
    RCC->BDCR |= RCC_BDCR_LSEON;
    while (!(RCC->BDCR & RCC_BDCR_LSERDY)) { }

    /* RTCSEL = 01 (LSE) and switch the RTC on */
    RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL_Msk)
              | (0x1u << RCC_BDCR_RTCSEL_Pos)
              | RCC_BDCR_RTCEN;
}

/* Period = (seconds) using ck_spre = 1 Hz. Valid 1..65536 s.
   WUCKSEL = 100b selects ck_spre; counter reload = seconds - 1. */
static void rtc_wakeup_start(uint32_t seconds)
{
    /* 1. Unlock RTC write protection */
    RTC->WPR = 0xCA;
    RTC->WPR = 0x53;

    /* 2. Disable the timer, then wait until it is safe to write WUTR */
    RTC->CR &= ~RTC_CR_WUTE;
    while (!(RTC->ISR & RTC_ISR_WUTWF)) { }   /* WUTWF = write allowed */

    /* 3. Reload value and clock source */
    RTC->WUTR = (seconds - 1u) & 0xFFFFu;
    RTC->CR = (RTC->CR & ~RTC_CR_WUCKSEL_Msk)
            | (0x4u << RTC_CR_WUCKSEL_Pos);   /* ck_spre (1 Hz)       */

    /* 4. Enable timer + its interrupt */
    RTC->CR |= RTC_CR_WUTE | RTC_CR_WUTIE;

    /* 5. Re-lock the RTC */
    RTC->WPR = 0xFF;

    /* 6. RTC wakeup is EXTI line 20 — unmask + rising edge so it can
          restart the clocks and vector the IRQ out of Stop. */
    EXTI->IMR1  |= (1u << 20);   /* interrupt mask   (IM20)  */
    EXTI->RTSR1 |= (1u << 20);   /* rising trigger   (RT20)  */

    NVIC_SetPriority(RTC_WKUP_IRQn, 2);
    NVIC_EnableIRQ(RTC_WKUP_IRQn);
}

volatile uint32_t ticks;

/* WUTF is an rc_w0 flag and is NOT under RTC write protection,
   so clearing it needs no WPR dance. Also clear EXTI line 20. */
void RTC_WKUP_IRQHandler(void)
{
    if (RTC->ISR & RTC_ISR_WUTF) {
        RTC->ISR &= ~RTC_ISR_WUTF;   /* acknowledge wakeup timer */
        ticks++;
    }
    EXTI->PR1 = (1u << 20);           /* clear pending (write 1)  */
}

int main(void)
{
    rtc_lse_init();
    rtc_wakeup_start(5);              /* wake every 5 seconds */

    for (;;) {
        /* --- enter Stop 2 --- */
        PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS_Msk)
                 | (0x2u << PWR_CR1_LPMS_Pos);
        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
        __DSB();
        __WFI();                     /* sleeps ~5 s, wakes in ISR */
        SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;

        /* Back on MSI ~4 MHz. Do a short task, then loop.
           Call restore_clock_after_stop() if you need full speed. */
    }
}

/* Assuming hrtc is initialised by HAL_RTC_Init() with LSE selected. */
RTC_HandleTypeDef hrtc;

/* 5-second period using ck_spre (1 Hz): counter = 5 - 1.
   The 4th arg (WakeUpAutoClr) = 0 disables the auto-reload output. */
HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 5u - 1u,
                            RTC_WAKEUPCLOCK_CKSPRE, 0u);

/* HAL enables EXTI line 20 + NVIC for you. Enter Stop 2: */
HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
SystemClock_Config();                /* rebuild clock after wake */

/* HAL supplies RTC_WKUP_IRQHandler -> HAL_RTCEx_WakeUpTimerIRQHandler.
   Handle the tick in the weak callback: */
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *h)
{
    (void)h;
    /* periodic work here */
}