RCC Clock Tree
MSI / HSI16 / HSE / PLL to 120 MHz

/* PWR is on APB1: its bus clock MUST be enabled before any PWR access */
RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
(void)RCC->APB1ENR1;                 /* read-back: guarantee the write landed */

/* Select voltage scaling Range 1 (VOS = 0b01) */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (0x1UL << PWR_CR1_VOS_Pos));

/* Enter Range 1 BOOST: clear R1MODE (reset value 1 = Range 1 normal, 80 MHz cap) */
PWR->CR5 &= ~PWR_CR5_R1MODE;

/* Wait until the internal regulator has settled at the new voltage */
while (PWR->SR2 & PWR_SR2_VOSF) { }   /* VOSF = 1 while voltage is changing */

/* Raise wait states BEFORE increasing the clock, then read back to confirm.
 * 120 MHz in Range 1 boost needs 5 WS. Writing LATENCY is not enough - the
 * value must be verified, because the flash accepts it only when stable.     */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_5WS);
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_5WS) { }

/* Prefetch + instruction cache + data cache: free performance on the L4+ */
FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;

/* Ensure the PLL source (MSI, 4 MHz by reset) is running and ready */
RCC->CR |= RCC_CR_MSION;
while (!(RCC->CR & RCC_CR_MSIRDY)) { }

/* PLLCFGR is writable only while the PLL is OFF */
RCC->CR &= ~RCC_CR_PLLON;
while (RCC->CR & RCC_CR_PLLRDY) { }

/* VCO   = (fIN / PLLM) * PLLN = (4 MHz / 1) * 60 = 240 MHz   (64..344 MHz OK)
 * SYSCLK= VCO / PLLR          = 240 MHz / 2      = 120 MHz
 * NOTE: the PLLM field holds (M - 1); the PLLR field encodes /2=0,/4=1,/6=2,/8=3 */
RCC->PLLCFGR =
      (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)   /* PLLSRC = 01 -> MSI              */
    | (0UL   << RCC_PLLCFGR_PLLM_Pos)     /* PLLM   = /1  (field = M-1 = 0)  */
    | (60UL  << RCC_PLLCFGR_PLLN_Pos)     /* PLLN   = x60                    */
    | (0UL   << RCC_PLLCFGR_PLLR_Pos)     /* PLLR   = /2  (field 0b00)       */
    | RCC_PLLCFGR_PLLREN;                 /* enable the PLLCLK (R) output    */

/* Start the PLL and wait for lock */
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) { }

/* HSE variant (e.g. Nucleo-L4R5ZI: 8 MHz from ST-LINK MCO, HSE bypass).
 * 8 MHz /1 x30 /2 = 120 MHz.  For a real crystal, drop HSEBYP.              */
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;      /* bypass = external clock in  */
while (!(RCC->CR & RCC_CR_HSERDY)) { }

RCC->PLLCFGR =
      (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)   /* PLLSRC = 11 -> HSE              */
    | (0UL   << RCC_PLLCFGR_PLLM_Pos)     /* /1  (8 MHz PLL input)           */
    | (30UL  << RCC_PLLCFGR_PLLN_Pos)     /* x30 -> VCO 240 MHz              */
    | (0UL   << RCC_PLLCFGR_PLLR_Pos)     /* /2  -> 120 MHz                  */
    | RCC_PLLCFGR_PLLREN;

/* Peripheral clock gating lives in the RCC AHBxENR / APBxENR registers.
 * A peripheral is DEAD (reads as 0, writes ignored) until its bit is set,
 * and you must read the register back before touching the peripheral so the
 * one- or two-cycle clock-enable latency has elapsed.                        */

RCC->AHB2ENR  |= RCC_AHB2ENR_GPIOAEN            /* GPIO ports A and B        */
              |  RCC_AHB2ENR_GPIOBEN;
RCC->APB1ENR1 |= RCC_APB1ENR1_TIM2EN            /* TIM2 (32-bit) on APB1     */
              |  RCC_APB1ENR1_USART2EN;
RCC->APB2ENR  |= RCC_APB2ENR_SYSCFGEN           /* SYSCFG + USART1 on APB2   */
              |  RCC_APB2ENR_USART1EN;
(void)RCC->APB2ENR;                             /* mandatory dummy read      */

#include "stm32l4xx.h"   /* umbrella header: pulls in stm32l4r5xx.h + CMSIS   */

/* ---------------------------------------------------------------------------
 * Bring the STM32L4R5 from its 4 MHz MSI reset state up to 120 MHz.
 *   MSI 4 MHz --> PLL (M=1, N=60, R=2) --> SYSCLK = 120 MHz
 *   HCLK = PCLK1 = PCLK2 = 120 MHz
 * Prerequisites handled in order: PWR boost, flash WS, PLL, bus, clock switch.
 * ------------------------------------------------------------------------- */
void SystemClock_Config_120MHz(void)
{
    /* 1. Power interface clock + Range 1 BOOST voltage scaling ------------- */
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
    (void)RCC->APB1ENR1;
    MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (0x1UL << PWR_CR1_VOS_Pos)); /* Range 1 */
    PWR->CR5 &= ~PWR_CR5_R1MODE;                                   /* boost   */
    while (PWR->SR2 & PWR_SR2_VOSF) { }

    /* 2. Flash: 5 wait states (verified) + prefetch and caches ------------- */
    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_5WS);
    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_5WS) { }
    FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;

    /* 3. Main PLL: MSI(4) /1 x60 /2 = 120 MHz ----------------------------- */
    RCC->CR |= RCC_CR_MSION;
    while (!(RCC->CR & RCC_CR_MSIRDY)) { }
    RCC->CR &= ~RCC_CR_PLLON;
    while (RCC->CR & RCC_CR_PLLRDY) { }
    RCC->PLLCFGR =
          (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)   /* MSI            */
        | (0UL   << RCC_PLLCFGR_PLLM_Pos)     /* /1  (M-1 = 0)  */
        | (60UL  << RCC_PLLCFGR_PLLN_Pos)     /* x60            */
        | (0UL   << RCC_PLLCFGR_PLLR_Pos)     /* /2             */
        | RCC_PLLCFGR_PLLREN;
    RCC->CR |= RCC_CR_PLLON;
    while (!(RCC->CR & RCC_CR_PLLRDY)) { }

    /* 4. Bus prescalers (all /1) then switch SYSCLK to the PLL ------------- */
    MODIFY_REG(RCC->CFGR,
               RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2,
               RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV1 | RCC_CFGR_PPRE2_DIV1);
    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) { }

    SystemCoreClock = 120000000UL;
}

int main(void)
{
    SystemClock_Config_120MHz();

    /* SYSCLK is now 120 MHz. Enable a couple of peripheral clocks as proof. */
    RCC->AHB2ENR  |= RCC_AHB2ENR_GPIOAEN;     /* GPIOA on AHB2               */
    RCC->APB1ENR1 |= RCC_APB1ENR1_USART2EN;   /* USART2 on APB1 (120 MHz)    */
    RCC->APB2ENR  |= RCC_APB2ENR_USART1EN;    /* USART1 on APB2 (120 MHz)    */
    (void)RCC->APB2ENR;                        /* barrier before first access */

    for (;;) { }
}

/* Same 120 MHz target using the STM32Cube HAL. Identical hardware sequence,
 * just wrapped: voltage boost -> flash latency (auto) -> PLL -> bus switch. */
void SystemClock_Config(void)
{
    RCC_OscInitTypeDef   osc = {0};
    RCC_ClkInitTypeDef   clk = {0};

    /* 1. Range 1 BOOST. HAL clears PWR_CR5.R1MODE and waits for VOSF. */
    __HAL_RCC_PWR_CLK_ENABLE();
    if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
        Error_Handler();

    /* 2. MSI 4 MHz -> PLL (M=1, N=60, R=2) = 120 MHz */
    osc.OscillatorType      = RCC_OSCILLATORTYPE_MSI;
    osc.MSIState            = RCC_MSI_ON;
    osc.MSIClockRange       = RCC_MSIRANGE_6;        /* 4 MHz */
    osc.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
    osc.PLL.PLLState        = RCC_PLL_ON;
    osc.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
    osc.PLL.PLLM            = 1;
    osc.PLL.PLLN            = 60;
    osc.PLL.PLLR            = 2;                      /* -> SYSCLK 120 MHz */
    osc.PLL.PLLP            = 2;
    osc.PLL.PLLQ            = 2;
    if (HAL_RCC_OscConfig(&osc) != HAL_OK)
        Error_Handler();

    /* 3. Buses all /1; HAL derives FLASH_LATENCY_5 from the 120 MHz target. */
    clk.ClockType      = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
                       | RCC_CLOCKTYPE_PCLK1  | RCC_CLOCKTYPE_PCLK2;
    clk.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
    clk.AHBCLKDivider  = RCC_SYSCLK_DIV1;
    clk.APB1CLKDivider = RCC_HCLK_DIV1;
    clk.APB2CLKDivider = RCC_HCLK_DIV1;
    if (HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_5) != HAL_OK)
        Error_Handler();
}