STM32L4R5
Chip overview & memory map

01 The device at a glance

The STM32L4R5 belongs to the STM32L4+ (L4 "plus") ultra-low-power family: an Arm Cortex-M4 with FPU running at 120 MHz, 2 Mbytes of flash and a large 640 Kbytes of SRAM, targeted at battery/energy-harvesting designs that still need graphics, audio and external-flash bandwidth. Compared to the classic STM32L4 (e.g. L476, RM0351) it adds a higher 120 MHz clock, more SRAM, two OctoSPI controllers, Chrom-ART (DMA2D), and — critically for driver code — a DMAMUX request router instead of fixed DMA channel mapping.

Headline specifications

Where the documentation lives

Every exact address, bit field and timing in this guide comes from ST's primary documents. Bookmark these — the reference manual and datasheet are the ground truth when a header macro is ambiguous:

02 Cortex-M4F core, clock tree & reaching 120 MHz

The core is a full Cortex-M4F: 3-stage pipeline, Thumb-2, hardware divide/MAC DSP instructions, a single-precision FPU, an 8-region MPU, the NVIC (interrupt controller, up to 16 priority levels) and a 24-bit SysTick down-counter clocked from HCLK. Flash accesses go through the ART Accelerator (prefetch + instruction/data cache) so zero-wait-state throughput is possible even at 120 MHz.

Clock sources

After reset the device runs from MSI at 4 MHz in voltage Range 1 (normal). To get to 120 MHz you must (1) select Range 1 boost, (2) raise flash wait states, then (3) engage the PLL — in that order.

Voltage scaling & flash wait states

120 MHz is only legal in Range 1 boost mode (PWR_CR5.R1MODE = 0). Flash latency must be set before the clock is raised. Wait-state limits in Range 1 boost:

In Range 1 normal the ceiling is 80 MHz (4 WS); in Range 2 it is only 26 MHz (3 WS). PLL constraints for the 120 MHz recipe:

Register-level clock init to 120 MHz (no HAL)

/* Bring SYSCLK to 120 MHz from the 16 MHz HSI using the main PLL.
 * Order is mandatory: boost + wait-states BEFORE raising the clock. */
#include "stm32l4r5xx.h"   /* CMSIS device header from STM32CubeL4 */

void sysclk_120mhz_hsi(void)
{
    /* 1. Turn on HSI16 and wait until it is stable */
    RCC->CR |= RCC_CR_HSION;
    while (!(RCC->CR & RCC_CR_HSIRDY)) { }

    /* 2. Enable the power interface clock, select Range 1, then Range-1 BOOST */
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS) | PWR_CR1_VOS_0;  /* VOS = 01 = Range 1 */
    while (PWR->SR2 & PWR_SR2_VOSF) { }                     /* wait regulator ready */
    PWR->CR5 &= ~PWR_CR5_R1MODE;                           /* 0 = boost: unlocks 120 MHz */

    /* 3. Flash: 5 wait states for 120 MHz, enable prefetch + I/D cache (ART) */
    FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY) | FLASH_ACR_LATENCY_5WS
               | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;

    /* 4. PLL: 16MHz /2 = 8MHz ref, *30 = 240MHz VCO, /2 = 120MHz SYSCLK.
     *    Note: the PLLM field is encoded as (divider - 1), so /2 -> 1. */
    RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSI
                 | (1u  << RCC_PLLCFGR_PLLM_Pos)   /* PLLM = /2  */
                 | (30u << RCC_PLLCFGR_PLLN_Pos)   /* PLLN = x30 */
                 | (0u  << RCC_PLLCFGR_PLLR_Pos)   /* PLLR = /2  */
                 | RCC_PLLCFGR_PLLREN;             /* enable PLLCLK (R) output */

    RCC->CR |= RCC_CR_PLLON;
    while (!(RCC->CR & RCC_CR_PLLRDY)) { }

    /* 5. Bus prescalers: AHB/1, APB1/1, APB2/1 (all valid up to 120 MHz) */
    RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2);

    /* 6. Switch SYSCLK to the PLL and wait for the hardware to confirm */
    RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) { }

    SystemCoreClock = 120000000u;  /* keep the CMSIS global in sync */
}

Same thing with the HAL

/* Equivalent 120 MHz setup with the STM32L4xx HAL. HAL takes the human
 * PLLM value (2), not the register-encoded value, and does the -1 for you. */
void SystemClock_Config(void)
{
    RCC_OscInitTypeDef osc = {0};
    RCC_ClkInitTypeDef clk = {0};

    /* Range 1 BOOST voltage scaling is required for 120 MHz */
    HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

    osc.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
    osc.HSIState            = RCC_HSI_ON;
    osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
    osc.PLL.PLLState        = RCC_PLL_ON;
    osc.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
    osc.PLL.PLLM            = 2;                /* 16 / 2 = 8 MHz  */
    osc.PLL.PLLN            = 30;               /* 8 * 30 = 240 MHz VCO */
    osc.PLL.PLLR            = RCC_PLLR_DIV2;    /* 240 / 2 = 120 MHz */
    osc.PLL.PLLQ            = RCC_PLLQ_DIV2;
    osc.PLL.PLLP            = RCC_PLLP_DIV2;
    HAL_RCC_OscConfig(&osc);

    clk.ClockType      = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
                       | RCC_CLOCKTYPE_PCLK1  | RCC_CLOCKTYPE_PCLK2;
    clk.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
    clk.AHBCLKDivider  = RCC_SYSCLK_DIV1;
    clk.APB1CLKDivider = RCC_HCLK_DIV1;
    clk.APB2CLKDivider = RCC_HCLK_DIV1;
    HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_5);  /* 5 WS */
}

03 Memory map & memory regions

Like every Cortex-M, the L4R5 uses the fixed 4 GB Armv7-M address space. Code lives in the low gigabyte (reached over the fast I-Code/D-Code buses), SRAM and peripherals sit at 0x2000_0000 and 0x4000_0000, external memories map into 0x6000_0000–0x9FFF_FFFF, and the private peripheral block (NVIC/SysTick/SCB) is at 0xE000_0000.

Top-level memory map

SRAM1 / SRAM2 / SRAM3 in detail

Because SRAM1+SRAM2+SRAM3 are contiguous (0x2000_0000 up to 0x2009_FFFF), a linker script can treat the 640 KB as one RAM region — but if you rely on Standby retention or parity you must keep those objects inside the SRAM2 window.

04 Bus matrix & bus masters

The L4R5 is not a single-master CPU bus — it is a multi-layer AHB bus matrix. Several masters (the CPU plus DMA engines) can reach several slaves concurrently, which is exactly why DMA can move data while the core keeps executing. Understanding who is a master matters when you debug a stalled transfer or a bus-contention slowdown.

Masters (initiators)

Slaves (targets) & the DMAMUX

Slaves include the flash interface, SRAM1/2/3, the four peripheral buses (APB1, APB2, AHB1, AHB2), the FMC and the two OctoSPI controllers. On the L4+ every DMA channel's trigger source is chosen through DMAMUX1: you write a request-line ID into DMAMUX1_CxCR.DMAREQ_ID rather than using the fixed per-channel CSELR tables of the classic STM32L4. Any peripheral request can go to any of the 14 channels.

05 Peripheral inventory & base addresses

The L4R5 is feature-dense. Below is the full peripheral count (from DS12023) followed by the base addresses you will hard-code or reach through CMSIS macros. Exact per-instance addresses always come from RM0432's "Memory map and register boundary addresses" table.

Peripheral count

Key base addresses (CMSIS-confirmed)

06 Packages & part-number decoding

A full ordering code such as STM32L4R5ZIT6 encodes everything: family, line, pin count/package, flash size, temperature range and packing. The two letters right after L4R5 are the ones you decode most often — pin/package and flash size.

Ordering-scheme letters (per DS12023)

So STM32L4R5ZI = LQFP144 + 2 MB, STM32L4R5VI = LQFP100 + 2 MB, STM32L4R5QI = UFBGA132 + 2 MB, and STM32L4R5AI = UFBGA169 + 2 MB. The Nucleo-144 board (NUCLEO-L4R5ZI) uses the LQFP144 part.

Package trade-offs

07 Boot modes & option bytes

On reset the CPU reads the initial stack pointer from address 0x0000_0000 and the reset vector from 0x0000_0004. What physically sits at 0x0000_0000 is chosen by the boot configuration — a combination of the BOOT0 input and the nBOOT1 option bit.

Boot memory selection (RM0432)

Where BOOT0 comes from is itself an option: nSWBOOT0 = 1 (factory default) takes BOOT0 from the physical PH3/BOOT0 pin; nSWBOOT0 = 0 takes it from the nBOOT0 option bit, letting you fix the boot source in software with no pull resistor. The BOOT0 pin level is latched a few SYSCLK cycles after reset release.

Option bytes at a glance

Option bytes are non-volatile configuration loaded into the read-only FLASH_OPTR shadow register at reset. Physical copies live at 0x1FFF_7800 (bank 1) and 0x1FFF_F800 (bank 2). Key fields inside FLASH_OPTR:

Reprogramming an option byte (register level)

/* Set nSWBOOT0=0 (BOOT0 from option bit) and nBOOT0=1 (boot main flash)
 * so the board always boots the application even if BOOT0 pin floats high.
 * WARNING: OBL_LAUNCH reloads option bytes and RESETS the MCU. */
#define FLASH_KEY1    0x45670123u
#define FLASH_KEY2    0xCDEF89ABu
#define FLASH_OPTKEY1 0x08192A3Bu
#define FLASH_OPTKEY2 0x4C5D6E7Fu

void boot_from_flash_fixed(void)
{
    while (FLASH->SR & FLASH_SR_BSY) { }

    /* 1. Unlock the flash control register (FLASH_CR) */
    if (FLASH->CR & FLASH_CR_LOCK) {
        FLASH->KEYR = FLASH_KEY1;
        FLASH->KEYR = FLASH_KEY2;
    }
    /* 2. Unlock the option-byte programming */
    FLASH->OPTKEYR = FLASH_OPTKEY1;
    FLASH->OPTKEYR = FLASH_OPTKEY2;

    /* 3. Modify the FLASH_OPTR shadow */
    FLASH->OPTR &= ~FLASH_OPTR_nSWBOOT0;   /* BOOT0 taken from nBOOT0 bit */
    FLASH->OPTR |=  FLASH_OPTR_nBOOT0;      /* nBOOT0 = 1 -> main flash */

    /* 4. Commit, wait, then reload option bytes (this triggers a reset) */
    FLASH->CR |= FLASH_CR_OPTSTRT;
    while (FLASH->SR & FLASH_SR_BSY) { }
    FLASH->CR |= FLASH_CR_OBL_LAUNCH;       /* system reset on completion */
}

08 Gotchas & common mistakes

The bugs below account for most "it hard-faults on my L4R5" reports. They come from the L4+ differences (boost mode, DMAMUX, AHB2 GPIO) that trip up code copied from other STM32 lines.