STM32L4R5 USART / LPUART
Poll · IRQ · DMA

#include "stm32l4r5xx.h"   /* CMSIS device header; define STM32L4R5xx in the build */
#include <stdint.h>

/* Put one pin into Alternate-Function mode: MODER=10, very-high speed,
   pull-up, and program the 4-bit AF selector in AFR[0] (pins 0-7) or AFR[1] (8-15). */
static void gpio_af(GPIO_TypeDef *port, uint32_t pin, uint32_t af)
{
    port->MODER   = (port->MODER   & ~(3u  << (pin * 2)))       | (2u << (pin * 2));
    port->OSPEEDR = (port->OSPEEDR |  (3u  << (pin * 2)));               /* very high */
    port->PUPDR   = (port->PUPDR   & ~(3u  << (pin * 2)))       | (1u << (pin * 2)); /* pull-up */
    port->OTYPER &= ~(1u << pin);                                        /* push-pull */
    port->AFR[pin >> 3] = (port->AFR[pin >> 3] & ~(0xFu << ((pin & 7) * 4)))
                        | (af << ((pin & 7) * 4));
}

USARTDIV = f_CK / baud            (rounded to nearest integer)
BRR      = USARTDIV               (all 16 bits used directly)

/* e.g. 80 MHz / 115200 = 694.44 -> BRR = 694 (0x02B6), error +0.06% */
USART2->BRR = (f_CK + baud/2) / baud;   /* rounded integer divide */

USARTDIV   = 2 * f_CK / baud                        (rounded)
BRR[15:4]  = USARTDIV[15:4]
BRR[3]     = 0                                      (reserved, keep clear)
BRR[2:0]   = USARTDIV[3:0] >> 1

/* helper */
static uint32_t brr_over8(uint32_t fck, uint32_t baud)
{
    uint32_t div = (2u * fck + baud / 2u) / baud;   /* USARTDIV, rounded */
    return (div & 0xFFF0u) | ((div & 0x000Fu) >> 1);
}
/* set OVER8 in CR1 (only while UE=0), then write BRR */
USART2->CR1 |= USART_CR1_OVER8;
USART2->BRR  = brr_over8(80000000u, 921600u);       /* -> 0x00A7 */

LPUART_BRR = (256 * f_CK) / baud          /* 20-bit; must be >= 0x300 */

/* LSE (32768 Hz) @ 9600 baud:  256*32768/9600 = 874 = 0x36A  (valid) */
LPUART1->BRR = (uint32_t)(((uint64_t)256 * 32768u) / 9600u);

/* HSI16 (16 MHz) @ 115200:     256*16e6/115200 = 35556 = 0x8AE4 */
LPUART1->BRR = (uint32_t)(((uint64_t)256 * 16000000u) / 115200u);

#include "stm32l4r5xx.h"
#include <stdint.h>

/* gpio_af() from section 02 is assumed available */

void uart2_init(uint32_t fck_hz, uint32_t baud)
{
    /* 1. Clocks: GPIOA + USART2 */
    RCC->AHB2ENR  |= RCC_AHB2ENR_GPIOAEN;
    RCC->APB1ENR1 |= RCC_APB1ENR1_USART2EN;

    /* 2. Kernel clock = PCLK1 (00 = reset default); fck_hz must equal PCLK1 then */
    RCC->CCIPR &= ~RCC_CCIPR_USART2SEL;

    /* 3. Pins: PA2 = USART2_TX (AF7), PA3 = USART2_RX (AF7) */
    gpio_af(GPIOA, 2, 7);
    gpio_af(GPIOA, 3, 7);

    /* 4. Program while disabled */
    USART2->CR1 = 0;                 /* 8N1, OVER16, FIFO off, no interrupts */
    USART2->CR2 = 0;                 /* STOP = 1 bit */
    USART2->CR3 = 0;
    USART2->BRR = (fck_hz + baud / 2u) / baud;   /* OVER16 rounded divide */

    /* 5. Enable peripheral, then TX + RX */
    USART2->CR1 |= USART_CR1_UE;
    USART2->CR1 |= USART_CR1_TE | USART_CR1_RE;
}

void uart2_putc(uint8_t c)
{
    while (!(USART2->ISR & USART_ISR_TXE_TXFNF)) { }   /* TDR empty? */
    USART2->TDR = c;                                   /* write clears TXE */
}

uint8_t uart2_getc(void)
{
    while (!(USART2->ISR & USART_ISR_RXNE_RXFNE)) {
        if (USART2->ISR & USART_ISR_ORE)               /* recover from overrun */
            USART2->ICR = USART_ICR_ORECF;
    }
    return (uint8_t)USART2->RDR;                        /* read clears RXNE */
}

void uart2_puts(const char *s)
{
    while (*s) uart2_putc((uint8_t)*s++);
    while (!(USART2->ISR & USART_ISR_TC)) { }           /* let last bit leave the wire */
    USART2->ICR = USART_ICR_TCCF;                       /* clear TC */
}

int main(void)
{
    /* assumes SystemClock already at 80 MHz and PCLK1 = 80 MHz */
    uart2_init(80000000u, 115200u);
    uart2_puts("STM32L4R5 USART2 up\r\n");
    for (;;) uart2_putc(uart2_getc());   /* echo */
}

#include "stm32l4r5xx.h"
#include <stdint.h>

#define TXQ_SIZE 256u
static volatile uint8_t  txq[TXQ_SIZE];
static volatile uint16_t tx_head, tx_tail;     /* head=write, tail=read (ISR) */

#define RXQ_SIZE 256u
static volatile uint8_t  rxq[RXQ_SIZE];
static volatile uint16_t rx_head, rx_tail;

void uart2_irq_init(uint32_t fck_hz, uint32_t baud)
{
    RCC->AHB2ENR  |= RCC_AHB2ENR_GPIOAEN;
    RCC->APB1ENR1 |= RCC_APB1ENR1_USART2EN;
    gpio_af(GPIOA, 2, 7);
    gpio_af(GPIOA, 3, 7);

    USART2->CR1 = 0;
    USART2->CR2 = 0;
    USART2->CR3 = 0;
    USART2->BRR = (fck_hz + baud / 2u) / baud;

    USART2->CR1 |= USART_CR1_RXNEIE_RXFNEIE;    /* IRQ on every received byte */
    USART2->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;

    NVIC_SetPriority(USART2_IRQn, 6);
    NVIC_EnableIRQ(USART2_IRQn);
}

/* Queue a byte for transmission and kick the TXE interrupt. */
void uart2_send(uint8_t c)
{
    uint16_t next = (uint16_t)((tx_head + 1u) % TXQ_SIZE);
    while (next == tx_tail) { }                 /* buffer full: wait (or drop) */
    txq[tx_head] = c;
    tx_head = next;
    USART2->CR1 |= USART_CR1_TXEIE_TXFNFIE;     /* arm TXE IRQ */
}

/* Non-blocking receive: returns -1 if empty. */
int uart2_recv(void)
{
    if (rx_tail == rx_head) return -1;
    uint8_t c = rxq[rx_tail];
    rx_tail = (uint16_t)((rx_tail + 1u) % RXQ_SIZE);
    return c;
}

void USART2_IRQHandler(void)
{
    uint32_t isr = USART2->ISR;

    /* --- RX --- */
    if (isr & USART_ISR_ORE)                     /* clear overrun, keep going */
        USART2->ICR = USART_ICR_ORECF;
    if (isr & USART_ISR_RXNE_RXFNE) {
        uint8_t c = (uint8_t)USART2->RDR;        /* reading RDR clears RXNE */
        uint16_t next = (uint16_t)((rx_head + 1u) % RXQ_SIZE);
        if (next != rx_tail) { rxq[rx_head] = c; rx_head = next; }  /* else drop */
    }

    /* --- TX --- only act if TXE IRQ is actually enabled */
    if ((isr & USART_ISR_TXE_TXFNF) && (USART2->CR1 & USART_CR1_TXEIE_TXFNFIE)) {
        if (tx_tail != tx_head) {
            USART2->TDR = txq[tx_tail];          /* writing TDR clears TXE */
            tx_tail = (uint16_t)((tx_tail + 1u) % TXQ_SIZE);
        } else {
            USART2->CR1 &= ~USART_CR1_TXEIE_TXFNFIE;  /* nothing left: stop TXE storm */
        }
    }
}

#include "stm32l4r5xx.h"
#include <stdint.h>
#include <string.h>

#define RX_BUF 128u
static volatile uint8_t rx_dma[RX_BUF];

void uart2_dma_init(uint32_t fck_hz, uint32_t baud)
{
    RCC->AHB2ENR  |= RCC_AHB2ENR_GPIOAEN;
    RCC->APB1ENR1 |= RCC_APB1ENR1_USART2EN;
    RCC->AHB1ENR  |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN;  /* DMA + DMAMUX clocks */

    gpio_af(GPIOA, 2, 7);
    gpio_af(GPIOA, 3, 7);

    USART2->CR1 = 0;
    USART2->CR2 = 0;
    USART2->CR3 = USART_CR3_DMAT | USART_CR3_DMAR;    /* route TX+RX through DMA */
    USART2->BRR = (fck_hz + baud / 2u) / baud;
    USART2->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;

    /* ---- RX: DMA1_Channel6  (= DMAMUX1_Channel5), circular, periph->mem ---- */
    DMA1_Channel6->CCR   = 0;                         /* disable before config */
    DMA1_Channel6->CPAR  = (uint32_t)&USART2->RDR;
    DMA1_Channel6->CMAR  = (uint32_t)rx_dma;
    DMA1_Channel6->CNDTR = RX_BUF;
    DMAMUX1_Channel5->CCR = 26u;                      /* USART2_RX request */
    DMA1_Channel6->CCR = DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_EN;  /* DIR=0, 8-bit */
}

/* Blocking-start DMA transmit of a buffer on DMA1_Channel7 (= DMAMUX1_Channel6). */
void uart2_dma_send(const uint8_t *buf, uint16_t len)
{
    DMA1_Channel7->CCR = 0;                           /* stop channel */
    DMA1->IFCR = DMA_IFCR_CGIF7;                      /* clear ch7 flags */
    DMA1_Channel7->CPAR  = (uint32_t)&USART2->TDR;
    DMA1_Channel7->CMAR  = (uint32_t)buf;
    DMA1_Channel7->CNDTR = len;
    DMAMUX1_Channel6->CCR = 27u;                      /* USART2_TX request */
    USART2->ICR = USART_ICR_TCCF;                     /* clear stale TC */
    DMA1_Channel7->CCR = DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_EN;   /* mem->periph */
}

/* Call when the DMA TX transfer-complete flag is set to confirm the wire is idle. */
void uart2_dma_wait_done(void)
{
    while (!(DMA1->ISR & DMA_ISR_TCIF7)) { }          /* DMA moved all bytes */
    DMA1->IFCR = DMA_IFCR_CTCIF7;
    DMA1_Channel7->CCR &= ~DMA_CCR_EN;
    while (!(USART2->ISR & USART_ISR_TC)) { }         /* last stop bit really left */
    USART2->ICR = USART_ICR_TCCF;
}

#include "stm32l4xx_hal.h"

UART_HandleTypeDef huart2;

void uart2_hal_init(void)
{
    __HAL_RCC_GPIOA_CLK_ENABLE();
    __HAL_RCC_USART2_CLK_ENABLE();

    GPIO_InitTypeDef g = {0};
    g.Pin       = GPIO_PIN_2 | GPIO_PIN_3;   /* PA2 TX, PA3 RX */
    g.Mode      = GPIO_MODE_AF_PP;
    g.Pull      = GPIO_PULLUP;
    g.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
    g.Alternate = GPIO_AF7_USART2;
    HAL_GPIO_Init(GPIOA, &g);

    huart2.Instance                    = USART2;
    huart2.Init.BaudRate               = 115200;
    huart2.Init.WordLength             = UART_WORDLENGTH_8B;   /* 8 data bits */
    huart2.Init.StopBits               = UART_STOPBITS_1;
    huart2.Init.Parity                 = UART_PARITY_NONE;
    huart2.Init.Mode                   = UART_MODE_TX_RX;
    huart2.Init.HwFlowCtl              = UART_HWCONTROL_NONE;
    huart2.Init.OverSampling           = UART_OVERSAMPLING_16;
    huart2.Init.OneBitSampling         = UART_ONE_BIT_SAMPLE_DISABLE;
    huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
    if (HAL_UART_Init(&huart2) != HAL_OK) { while (1) { } }
}

/* ---- Blocking (polling) ---- */
void demo_poll(void)
{
    uint8_t rx;
    HAL_UART_Transmit(&huart2, (uint8_t *)"hi\r\n", 4, HAL_MAX_DELAY);
    HAL_UART_Receive(&huart2, &rx, 1, HAL_MAX_DELAY);
}

/* ---- Interrupt: arm a 1-byte receive, refill in the callback ---- */
static uint8_t rx_byte;
void demo_it_start(void) { HAL_UART_Receive_IT(&huart2, &rx_byte, 1); }

void HAL_UART_RxCpltCallback(UART_HandleTypeDef *h)
{
    if (h->Instance == USART2) {
        HAL_UART_Transmit(&huart2, &rx_byte, 1, HAL_MAX_DELAY);  /* echo */
        HAL_UART_Receive_IT(&huart2, &rx_byte, 1);               /* re-arm */
    }
}

/* The HAL IRQ handler must be routed from the vector: */
void USART2_IRQHandler(void) { HAL_UART_IRQHandler(&huart2); }

#include "stm32l4r5xx.h"
#include <stdint.h>

void lpuart1_lp_init(void)
{
    /* 1. PWR clock, then enable VDDIO2 so Port G[15:2] (PG7/PG8) works */
    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
    PWR->CR2 |= PWR_CR2_IOSV;

    /* 2. Turn on LSE (needs backup-domain write access) */
    PWR->CR1 |= PWR_CR1_DBP;                 /* unlock RTC/backup domain */
    RCC->BDCR |= RCC_BDCR_LSEON;
    while (!(RCC->BDCR & RCC_BDCR_LSERDY)) { }

    /* 3. GPIOG + LPUART1 clocks */
    RCC->AHB2ENR  |= RCC_AHB2ENR_GPIOGEN;
    RCC->APB1ENR2 |= RCC_APB1ENR2_LPUART1EN;

    /* 4. LPUART1 kernel clock = LSE (11) */
    RCC->CCIPR = (RCC->CCIPR & ~RCC_CCIPR_LPUART1SEL)
               | (3u << RCC_CCIPR_LPUART1SEL_Pos);

    /* 5. Pins: PG7 = LPUART1_TX (AF8), PG8 = LPUART1_RX (AF8) */
    gpio_af(GPIOG, 7, 8);
    gpio_af(GPIOG, 8, 8);

    /* 6. Configure while disabled: 9600 8N1 from LSE */
    LPUART1->CR1 = 0;
    LPUART1->CR2 = 0;
    LPUART1->CR3 = 0;
    LPUART1->BRR = (uint32_t)(((uint64_t)256 * 32768u) / 9600u);   /* = 0x36A */

    /* 7. Wake-from-Stop plumbing */
    LPUART1->CR3 |= (3u << USART_CR3_WUS_Pos);   /* WUS=11: wake on RXNE */
    LPUART1->CR3 |= USART_CR3_WUFIE;             /* wake-up interrupt */
    LPUART1->CR1 |= USART_CR1_UESM;              /* keep LPUART clocked in Stop */

    LPUART1->CR1 |= USART_CR1_UE;
    LPUART1->CR1 |= USART_CR1_TE | USART_CR1_RE;

    /* 8. Route the wake-up line: EXTI line 28 = LPUART1 wakeup */
    EXTI->IMR1  |= EXTI_IMR1_IM28;               /* unmask */
    EXTI->RTSR1 |= EXTI_RTSR1_RT28;              /* rising edge */
    NVIC_EnableIRQ(LPUART1_IRQn);
}

void LPUART1_IRQHandler(void)
{
    if (LPUART1->ISR & USART_ISR_WUF)            /* woke the core */
        LPUART1->ICR = USART_ICR_WUCF;
    if (LPUART1->ISR & USART_ISR_RXNE_RXFNE)
        (void)LPUART1->RDR;                      /* consume the byte */
}