STM32L4R5 SPI Master
CPOL/CPHA, FIFO & DMA

// GPIO port clocks (AHB2)
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;      // PA4..PA7 for SPI1

// SPI peripheral clocks
RCC->APB2ENR  |= RCC_APB2ENR_SPI1EN;      // SPI1  (bit 12, APB2)
RCC->APB1ENR1 |= RCC_APB1ENR1_SPI2EN;     // SPI2  (bit 14, APB1)
RCC->APB1ENR1 |= RCC_APB1ENR1_SPI3EN;     // SPI3  (bit 15, APB1)

// For DMA later (AHB1):
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN;

// Erratum-safe: read back after enabling a clock before using the block
(void)RCC->APB2ENR;

static void spi1_gpio_init(void)
{
    // MODER = 0b10 (alternate function) for PA5, PA6, PA7
    GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE6 | GPIO_MODER_MODE7);
    GPIOA->MODER |=  (2u << GPIO_MODER_MODE5_Pos)
                 |  (2u << GPIO_MODER_MODE6_Pos)
                 |  (2u << GPIO_MODER_MODE7_Pos);

    // Very-high-speed output (0b11) — needed above a few MHz
    GPIOA->OSPEEDR |= (3u << GPIO_OSPEEDR_OSPEED5_Pos)
                   |  (3u << GPIO_OSPEEDR_OSPEED6_Pos)
                   |  (3u << GPIO_OSPEEDR_OSPEED7_Pos);

    // Push-pull (default), no pull-up/down (MISO may want a pull if slave tristates)
    GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD6 | GPIO_PUPDR_PUPD7);

    // AFR[0] handles pins 0..7; write AF5 into the 4-bit nibble of each pin
    GPIOA->AFR[0] &= ~((0xFu << (5*4)) | (0xFu << (6*4)) | (0xFu << (7*4)));
    GPIOA->AFR[0] |=  ((5u   << (5*4)) | (5u   << (6*4)) | (5u   << (7*4)));

    // Chip-select on PA4 as a plain GPIO output, idle HIGH (software NSS)
    GPIOA->MODER &= ~GPIO_MODER_MODE4;
    GPIOA->MODER |=  (1u << GPIO_MODER_MODE4_Pos);  // general output
    GPIOA->BSRR   =  GPIO_BSRR_BS4;                 // deselect (drive high)
}

#include "stm32l4xx.h"

// ---- forward decl from §03 ----
static void spi1_gpio_init(void);

void spi1_master_init(void)
{
    // 1) Clocks
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
    RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
    (void)RCC->APB2ENR;               // read-back barrier

    spi1_gpio_init();                 // PA5/6/7 = AF5, PA4 = CS output

    // 2) Configure with SPE = 0
    SPI1->CR1 = 0;                     // clear: CPOL=0, CPHA=0 (mode 0), MSB first
    SPI1->CR1 |= SPI_CR1_MSTR          // master
              |  SPI_CR1_SSM           // software NSS management
              |  SPI_CR1_SSI           // internal NSS high -> no MODF
              |  (3u << SPI_CR1_BR_Pos); // BR=011 -> PCLK2/16

    // 3) CR2: 8-bit frames, RXNE per byte, no DMA/IRQ yet
    SPI1->CR2 = (0x7u << SPI_CR2_DS_Pos) // DS=0111 -> 8-bit
             |  SPI_CR2_FRXTH;          // FRXTH=1 -> RXNE asserts at 8 bits

    // 4) Enable
    SPI1->CR1 |= SPI_CR1_SPE;
}

// One full-duplex byte: send tx, return the byte clocked in on MISO.
uint8_t spi1_txrx(uint8_t tx)
{
    while (!(SPI1->SR & SPI_SR_TXE)) { }        // wait TX space
    *(volatile uint8_t *)&SPI1->DR = tx;        // 8-bit write (critical!)
    while (!(SPI1->SR & SPI_SR_RXNE)) { }        // wait for the echo
    return *(volatile uint8_t *)&SPI1->DR;      // 8-bit read
}

// Buffer transfer with manual chip-select (PA4).
void spi1_transfer(const uint8_t *tx, uint8_t *rx, uint32_t n)
{
    GPIOA->BSRR = GPIO_BSRR_BR4;                 // CS low (select)
    for (uint32_t i = 0; i < n; i++) {
        uint8_t out = tx ? tx[i] : 0xFF;        // 0xFF = dummy for reads
        uint8_t in  = spi1_txrx(out);
        if (rx) rx[i] = in;
    }
    // Wait until the shift register has fully drained before raising CS
    while (SPI1->SR & SPI_SR_BSY) { }
    GPIOA->BSRR = GPIO_BSRR_BS4;                 // CS high (deselect)
}

// While SPE = 0:
SPI1->CR2 = (0xFu << SPI_CR2_DS_Pos);   // DS=1111 -> 16-bit; FRXTH is ignored
SPI1->CR1 |= SPI_CR1_SPE;

uint16_t spi1_txrx16(uint16_t tx)
{
    while (!(SPI1->SR & SPI_SR_TXE)) { }
    SPI1->DR = tx;                       // 16-bit access is correct here
    while (!(SPI1->SR & SPI_SR_RXNE)) { }
    return SPI1->DR;
}

#include "stm32l4xx.h"

// Call once after spi1_master_init().
void spi1_dma_init(void)
{
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN;

    // Route request lines. DMAREQ_ID lives in bits [6:0]; other bits stay 0.
    DMAMUX1_Channel1->CCR = 10u;   // SPI1_RX -> DMA1_Channel2
    DMAMUX1_Channel2->CCR = 11u;   // SPI1_TX -> DMA1_Channel3
}

// Blocking full-duplex transfer of n bytes via DMA.
void spi1_dma_transfer(const uint8_t *tx, uint8_t *rx, uint16_t n)
{
    // ---- RX channel: peripheral -> memory (DIR = 0) ----
    DMA1_Channel2->CCR   = 0;                       // disable while configuring
    DMA1_Channel2->CPAR  = (uint32_t)&SPI1->DR;     // 8-bit peripheral reg
    DMA1_Channel2->CMAR  = (uint32_t)rx;
    DMA1_Channel2->CNDTR = n;
    DMA1_Channel2->CCR   = DMA_CCR_MINC             // increment memory
                         | DMA_CCR_TCIE;           // PSIZE/MSIZE = 00 (8-bit), DIR=0

    // ---- TX channel: memory -> peripheral (DIR = 1) ----
    DMA1_Channel3->CCR   = 0;
    DMA1_Channel3->CPAR  = (uint32_t)&SPI1->DR;
    DMA1_Channel3->CMAR  = (uint32_t)tx;
    DMA1_Channel3->CNDTR = n;
    DMA1_Channel3->CCR   = DMA_CCR_MINC | DMA_CCR_DIR;  // DIR=1 mem->periph

    GPIOA->BSRR = GPIO_BSRR_BR4;                    // CS low

    // Enable channels: RX first so it can never miss the first byte.
    DMA1_Channel2->CCR |= DMA_CCR_EN;
    DMA1_Channel3->CCR |= DMA_CCR_EN;

    // Enable the SPI DMA requests: RX before TX.
    SPI1->CR2 |= SPI_CR2_RXDMAEN;
    SPI1->CR2 |= SPI_CR2_TXDMAEN;

    // Wait for RX completion (RX finishing guarantees the frame is done).
    while (!(DMA1->ISR & DMA_ISR_TCIF2)) { }
    DMA1->IFCR = DMA_IFCR_CTCIF2;                   // clear TC flag

    // ---- Tear down in the correct order ----
    while (SPI1->SR & SPI_SR_BSY) { }
    SPI1->CR2 &= ~(SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
    DMA1_Channel2->CCR &= ~DMA_CCR_EN;
    DMA1_Channel3->CCR &= ~DMA_CCR_EN;

    GPIOA->BSRR = GPIO_BSRR_BS4;                    // CS high
}

#include "stm32l4xx_hal.h"

SPI_HandleTypeDef hspi1;
DMA_HandleTypeDef hdma_spi1_tx;
DMA_HandleTypeDef hdma_spi1_rx;

void MX_SPI1_Init(void)
{
    hspi1.Instance               = SPI1;
    hspi1.Init.Mode              = SPI_MODE_MASTER;
    hspi1.Init.Direction         = SPI_DIRECTION_2LINES;      // full-duplex
    hspi1.Init.DataSize          = SPI_DATASIZE_8BIT;
    hspi1.Init.CLKPolarity       = SPI_POLARITY_LOW;          // CPOL = 0
    hspi1.Init.CLKPhase          = SPI_PHASE_1EDGE;           // CPHA = 0  (mode 0)
    hspi1.Init.NSS               = SPI_NSS_SOFT;              // software NSS
    hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;  // PCLK2/16
    hspi1.Init.FirstBit          = SPI_FIRSTBIT_MSB;
    hspi1.Init.TIMode            = SPI_TIMODE_DISABLE;
    hspi1.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE;
    hspi1.Init.CRCPolynomial     = 7;
    hspi1.Init.CRCLength         = SPI_CRC_LENGTH_DATASIZE;
    hspi1.Init.NSSPMode          = SPI_NSS_PULSE_DISABLE;
    if (HAL_SPI_Init(&hspi1) != HAL_OK) { Error_Handler(); }
}

// Called automatically by HAL_SPI_Init() — configure clocks, pins, DMA here.
void HAL_SPI_MspInit(SPI_HandleTypeDef *spi)
{
    if (spi->Instance != SPI1) return;

    __HAL_RCC_SPI1_CLK_ENABLE();
    __HAL_RCC_GPIOA_CLK_ENABLE();
    __HAL_RCC_DMA1_CLK_ENABLE();
    __HAL_RCC_DMAMUX1_CLK_ENABLE();

    GPIO_InitTypeDef g = {0};
    g.Pin       = GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;   // SCK/MISO/MOSI
    g.Mode      = GPIO_MODE_AF_PP;
    g.Pull      = GPIO_NOPULL;
    g.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
    g.Alternate = GPIO_AF5_SPI1;
    HAL_GPIO_Init(GPIOA, &g);

    // TX: DMA1_Channel3
    hdma_spi1_tx.Instance                 = DMA1_Channel3;
    hdma_spi1_tx.Init.Request             = DMA_REQUEST_SPI1_TX;   // ID 11
    hdma_spi1_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
    hdma_spi1_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
    hdma_spi1_tx.Init.MemInc              = DMA_MINC_ENABLE;
    hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_spi1_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
    hdma_spi1_tx.Init.Mode                = DMA_NORMAL;
    hdma_spi1_tx.Init.Priority            = DMA_PRIORITY_HIGH;
    HAL_DMA_Init(&hdma_spi1_tx);
    __HAL_LINKDMA(spi, hdmatx, hdma_spi1_tx);

    // RX: DMA1_Channel2
    hdma_spi1_rx.Instance                 = DMA1_Channel2;
    hdma_spi1_rx.Init.Request             = DMA_REQUEST_SPI1_RX;   // ID 10
    hdma_spi1_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
    hdma_spi1_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
    hdma_spi1_rx.Init.MemInc              = DMA_MINC_ENABLE;
    hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_spi1_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
    hdma_spi1_rx.Init.Mode                = DMA_NORMAL;
    hdma_spi1_rx.Init.Priority            = DMA_PRIORITY_HIGH;
    HAL_DMA_Init(&hdma_spi1_rx);
    __HAL_LINKDMA(spi, hdmarx, hdma_spi1_rx);

    HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
    HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
}

// The DMA IRQs must forward into the HAL DMA handler:
void DMA1_Channel2_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_rx); }
void DMA1_Channel3_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_spi1_tx); }

uint8_t tx[4] = { 0x9F, 0xFF, 0xFF, 0xFF };   // e.g. flash "read ID"
uint8_t rx[4];

// Software NSS -> toggle your CS GPIO around the call.
void read_id(void)
{
    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_RESET);   // CS low

    // Blocking full-duplex:
    HAL_SPI_TransmitReceive(&hspi1, tx, rx, 4, HAL_MAX_DELAY);

    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);     // CS high
}

// Non-blocking full-duplex over DMA:
void read_id_dma(void)
{
    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_RESET);
    HAL_SPI_TransmitReceive_DMA(&hspi1, tx, rx, 4);
    // return; completion is signalled in the callback below.
}

// Fires when the DMA full-duplex transfer completes.
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *spi)
{
    if (spi->Instance == SPI1)
        HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET); // CS high
}

void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *spi)
{
    // Inspect spi->ErrorCode: HAL_SPI_ERROR_OVR / _MODF / _DMA ...
}

static void spi1_disable(void)
{
    while ((SPI1->SR & SPI_SR_FTLVL) != 0) { }   // 1) TX FIFO drained
    while (SPI1->SR & SPI_SR_BSY)        { }      // 2) last frame shifted out
    SPI1->CR1 &= ~SPI_CR1_SPE;                    // 3) disable

    // 4) flush any remaining RX bytes
    while ((SPI1->SR & SPI_SR_FRLVL) != 0)
        (void)*(volatile uint8_t *)&SPI1->DR;
}