DMA & DMAMUX
Request Routing on STM32L4+

#include "stm32l4r5xx.h"

/* RCC->AHB1ENR: DMA1EN=bit0, DMA2EN=bit1, DMAMUX1EN=bit2 */
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN      /* controller  */
             |  RCC_AHB1ENR_DMAMUX1EN;  /* the router — do NOT forget */
(void)RCC->AHB1ENR;                     /* read-back: let the clock settle */

#include "stm32l4r5xx.h"
#include <stdint.h>

/* DMAMUX CxCR that drives a given DMA channel (ch = 1..7).
 *   DMA1 Ch1..7 -> DMAMUX1 Channel 0..6
 *   DMA2 Ch1..7 -> DMAMUX1 Channel 7..13                     */
static inline DMAMUX_Channel_TypeDef *dmamux_for(DMA_TypeDef *dma, uint8_t ch)
{
    uint32_t idx = (dma == DMA2 ? 7u : 0u) + (uint32_t)(ch - 1u);
    return DMAMUX1_Channel0 + idx;      /* 4 bytes per CxCR */
}

/* Register block for DMA channel ch (1..7). */
static inline DMA_Channel_TypeDef *dma_ch(DMA_TypeDef *dma, uint8_t ch)
{
    uint32_t base = (uint32_t)dma + 0x08u + 0x14u * (uint32_t)(ch - 1u);
    return (DMA_Channel_TypeDef *)base;
}

/* One-shot or circular transfer setup. `ccr_flags` carries DIR, MINC,
 * PSIZE/MSIZE, PL, CIRC and any *IE bits — but NOT the EN bit.        */
void dma_setup(DMA_TypeDef *dma, uint8_t ch, uint8_t request,
               volatile void *periph, void *mem, uint16_t count,
               uint32_t ccr_flags)
{
    DMA_Channel_TypeDef *c = dma_ch(dma, ch);

    c->CCR &= ~DMA_CCR_EN;                     /* (2) disable   */
    while (c->CCR & DMA_CCR_EN) { }            /*     wait off  */

    dma->IFCR = 0xFu << (4u * (ch - 1u));      /* (3) clear GIF/TCIF/HTIF/TEIF */

    c->CPAR  = (uint32_t)periph;               /* (4) periph addr */
    c->CMAR  = (uint32_t)mem;                  /* (5) buffer addr */
    c->CNDTR = count;                          /* (6) item count  */

    dmamux_for(dma, ch)->CCR = request;        /* (7) route request */

    c->CCR = ccr_flags;                        /* (8) config, EN=0   */
    c->CCR |= DMA_CCR_EN;                       /* (9) go             */
}

#include "stm32l4r5xx.h"
#include <stdint.h>

#define NUM_CH   3u
static volatile uint16_t adc_buf[NUM_CH];   /* 12-bit samples, halfwords */

static void clocks_init(void)
{
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN;
    RCC->AHB2ENR |= RCC_AHB2ENR_ADCEN;       /* ADC is on AHB2 */
    (void)RCC->AHB2ENR;

    /* Clock the ADC synchronously from HCLK/4 (CKMODE=11) so no
       RCC ADCSEL kernel-clock selection is required.                */
    ADC1_COMMON->CCR |= ADC_CCR_CKMODE_0 | ADC_CCR_CKMODE_1;  /* 11 */
}

static void adc_enable(void)
{
    ADC1->CR &= ~ADC_CR_DEEPPWD;             /* leave deep-power-down   */
    ADC1->CR |= ADC_CR_ADVREGEN;             /* turn on ADC regulator   */
    for (volatile int i = 0; i < 4000; i++) { }  /* > t_ADCVREG_STUP (~20us) */

    ADC1->CR &= ~ADC_CR_ADCALDIF;            /* single-ended calibration */
    ADC1->CR |= ADC_CR_ADCAL;
    while (ADC1->CR & ADC_CR_ADCAL) { }      /* wait for cal to finish   */

    ADC1->ISR = ADC_ISR_ADRDY;              /* clear ADRDY (rc_w1)      */
    ADC1->CR |= ADC_CR_ADEN;                 /* enable the ADC           */
    while (!(ADC1->ISR & ADC_ISR_ADRDY)) { }
}

static void adc_dma_init(void)
{
    /* --- regular sequence: 3 conversions, channels 1,2,3 --- */
    ADC1->SQR1 = ((NUM_CH - 1u) << ADC_SQR1_L_Pos)  /* L = length-1 */
               | (1u << ADC_SQR1_SQ1_Pos)
               | (2u << ADC_SQR1_SQ2_Pos)
               | (3u << ADC_SQR1_SQ3_Pos);
    ADC1->SMPR1 = 0x3FFFFFFFu;               /* long sample time, ch0..9 */

    /* continuous + DMA + circular DMA (DMACFG=1) + overrun overwrite */
    ADC1->CFGR = ADC_CFGR_CONT | ADC_CFGR_DMAEN
               | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD;

    /* --- DMA1 Channel 1: ADC1->DR (16-bit) -> adc_buf, circular --- */
    DMA_Channel_TypeDef *c = DMA1_Channel1;
    c->CCR &= ~DMA_CCR_EN;
    while (c->CCR & DMA_CCR_EN) { }
    DMA1->IFCR = 0xFu;                        /* clear ch1 flags */

    c->CPAR  = (uint32_t)&ADC1->DR;          /* source: ADC data reg */
    c->CMAR  = (uint32_t)adc_buf;             /* dest: SRAM buffer    */
    c->CNDTR = NUM_CH;                        /* 3 halfword items     */

    DMAMUX1_Channel0->CCR = 5u;              /* DMA1 Ch1 = mux0, req = ADC1 */

    c->CCR = DMA_CCR_MINC                     /* walk the buffer        */
           | DMA_CCR_CIRC                     /* wrap forever           */
           | DMA_CCR_PSIZE_0                  /* PSIZE=01 -> 16-bit     */
           | DMA_CCR_MSIZE_0                  /* MSIZE=01 -> 16-bit     */
           | DMA_CCR_PL_1;                    /* priority = high (10)   */
    /* DIR left 0 = read from peripheral (P2M); PINC left 0 */
    c->CCR |= DMA_CCR_EN;                      /* enable channel         */
}

int main(void)
{
    clocks_init();
    adc_enable();
    adc_dma_init();

    ADC1->CR |= ADC_CR_ADSTART;               /* start regular conversions */

    for (;;) {
        /* adc_buf[0..2] refreshed continuously by DMA — read anytime. */
    }
}

#include "stm32l4r5xx.h"
#include <stdint.h>

#define RX_LEN 64u
static volatile uint8_t rx_buf[RX_LEN];   /* circular RX ring */

/* Assumes USART2 already has baud/framing set and UE/TE/RE enabled. */
void uart_dma_init(void)
{
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN;

    /* ---- RX: USART2->RDR -> rx_buf, circular ----
       DMA1 Ch6 == DMAMUX1 Channel 5, request 26 = USART2_RX */
    DMA1_Channel6->CCR &= ~DMA_CCR_EN;
    while (DMA1_Channel6->CCR & DMA_CCR_EN) { }
    DMA1->IFCR = 0xFu << (4u * (6u - 1u));    /* clear ch6 flags */

    DMA1_Channel6->CPAR  = (uint32_t)&USART2->RDR;
    DMA1_Channel6->CMAR  = (uint32_t)rx_buf;
    DMA1_Channel6->CNDTR = RX_LEN;
    DMAMUX1_Channel5->CCR = 26u;             /* USART2_RX */
    DMA1_Channel6->CCR = DMA_CCR_MINC | DMA_CCR_CIRC; /* 8-bit sizes = reset */
    DMA1_Channel6->CCR |= DMA_CCR_EN;

    /* ---- TX: only route the channel now (armed per message) ----
       DMA1 Ch7 == DMAMUX1 Channel 6, request 27 = USART2_TX */
    DMAMUX1_Channel6->CCR = 27u;             /* USART2_TX */

    /* Step 10: let USART generate DMA requests in both directions */
    USART2->CR3 |= USART_CR3_DMAT | USART_CR3_DMAR;
}

/* Fire a memory-to-peripheral transfer of `len` bytes. */
void uart_send_dma(const uint8_t *data, uint16_t len)
{
    DMA_Channel_TypeDef *c = DMA1_Channel7;

    c->CCR &= ~DMA_CCR_EN;
    while (c->CCR & DMA_CCR_EN) { }
    DMA1->IFCR = 0xFu << (4u * (7u - 1u));    /* clear ch7 flags */

    c->CPAR  = (uint32_t)&USART2->TDR;
    c->CMAR  = (uint32_t)data;
    c->CNDTR = len;
    c->CCR   = DMA_CCR_DIR                     /* memory -> peripheral */
            | DMA_CCR_MINC                     /* walk the buffer      */
            | DMA_CCR_TCIE;                    /* IRQ when done        */
    c->CCR  |= DMA_CCR_EN;
}

/* TX-complete: DMA1 Channel 7 (IRQn = 17). */
void DMA1_Channel7_IRQHandler(void)
{
    if (DMA1->ISR & DMA_ISR_TCIF7) {
        DMA1->IFCR = DMA_IFCR_CTCIF7;         /* ack TC */
        DMA1_Channel7->CCR &= ~DMA_CCR_EN;    /* stop the channel */
        /* For half-duplex/RS-485 wait for USART2->ISR & USART_ISR_TC
           before releasing the driver-enable line. */
    }
}

/* Bytes received so far into the ring = RX_LEN - remaining. */
uint16_t uart_rx_count(void)
{
    return (uint16_t)(RX_LEN - DMA1_Channel6->CNDTR);
}

#include "stm32l4xx_hal.h"

extern UART_HandleTypeDef huart2;   /* configured elsewhere (baud, pins) */
DMA_HandleTypeDef hdma_usart2_tx;

void uart2_tx_dma_init(void)
{
    __HAL_RCC_DMA1_CLK_ENABLE();
    __HAL_RCC_DMAMUX1_CLK_ENABLE();

    hdma_usart2_tx.Instance                 = DMA1_Channel7;
    hdma_usart2_tx.Init.Request             = DMA_REQUEST_USART2_TX; /* 27 */
    hdma_usart2_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
    hdma_usart2_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
    hdma_usart2_tx.Init.MemInc              = DMA_MINC_ENABLE;
    hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_usart2_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
    hdma_usart2_tx.Init.Mode                = DMA_NORMAL;
    hdma_usart2_tx.Init.Priority            = DMA_PRIORITY_HIGH;
    HAL_DMA_Init(&hdma_usart2_tx);

    __HAL_LINKDMA(&huart2, hdmatx, hdma_usart2_tx);  /* wire handle to UART */

    HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
}

/* Route the channel IRQ into the HAL DMA state machine. */
void DMA1_Channel7_IRQHandler(void)
{
    HAL_DMA_IRQHandler(huart2.hdmatx);
}

void app_send(const uint8_t *buf, uint16_t n)
{
    HAL_UART_Transmit_DMA(&huart2, (uint8_t *)buf, n);
}

#include "stm32l4r5xx.h"
#include <stdint.h>

#define BLK 128u
static volatile uint16_t stream[2u * BLK];   /* two half-buffers */
extern void process(const volatile uint16_t *half, uint32_t n);

void stream_irq_enable(void)
{
    /* CNDTR must be 2*BLK and CIRC set when the channel was configured. */
    DMA1_Channel1->CCR |= DMA_CCR_HTIE | DMA_CCR_TCIE | DMA_CCR_TEIE;
    NVIC_SetPriority(DMA1_Channel1_IRQn, 5);
    NVIC_EnableIRQ(DMA1_Channel1_IRQn);
}

void DMA1_Channel1_IRQHandler(void)
{
    uint32_t isr = DMA1->ISR;

    if (isr & DMA_ISR_HTIF1) {               /* first half ready  */
        DMA1->IFCR = DMA_IFCR_CHTIF1;         /* ack BEFORE work    */
        process(&stream[0], BLK);
    }
    if (isr & DMA_ISR_TCIF1) {               /* second half ready */
        DMA1->IFCR = DMA_IFCR_CTCIF1;
        process(&stream[BLK], BLK);
    }
    if (isr & DMA_ISR_TEIF1) {               /* bus / config error */
        DMA1->IFCR = DMA_IFCR_CTEIF1;
        /* channel auto-disables on TE — clear cause and re-init here */
    }
}