STM32L4R5 I2C
TIMINGR & master transfers.

// TIMINGR = PRESC[31:28] | SCLDEL[23:20] | SDADEL[19:16] | SCLH[15:8] | SCLL[7:0]
// 100 kHz @ 16 MHz: PRESC=3, SCLDEL=4, SDADEL=2, SCLH=0x0F, SCLL=0x13
uint32_t timingr = (3u  << 28)   // PRESC  -> tPRESC = 4/16MHz = 250 ns
                 | (4u  << 20)   // SCLDEL
                 | (2u  << 16)   // SDADEL
                 | (0x0Fu << 8)  // SCLH  -> 16*250ns = 4.0 us high
                 | (0x13u);       // SCLL  -> 20*250ns = 5.0 us low  => ~100 kHz
// timingr == 0x30420F13

// STM32L4R5 — CMSIS device header defines RCC, GPIOB, I2C1, and the *_Pos/_Msk macros.
// I2C1_SCL = PB8 (AF4), I2C1_SDA = PB9 (AF4). External 2.2k-4.7k pull-ups required.
#include "stm32l4r5xx.h"

void i2c1_init_400k(void)
{
    // 1) Kernel clock = HSI16 (fixed 16 MHz) so the RM0432 16 MHz TIMINGR values apply.
    RCC->CR |= RCC_CR_HSION;
    while (!(RCC->CR & RCC_CR_HSIRDY)) { }
    RCC->CCIPR = (RCC->CCIPR & ~RCC_CCIPR_I2C1SEL_Msk)
               | (0x2u << RCC_CCIPR_I2C1SEL_Pos);   // 10 = HSI16

    // 2) GPIOB clock, then PB8/PB9 -> AF mode, open-drain, very-high speed, weak pull-up.
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN;
    (void)RCC->AHB2ENR;                              // dummy read: let the clock settle

    GPIOB->MODER   = (GPIOB->MODER  & ~((3u<<(8*2)) | (3u<<(9*2))))
                   | (2u<<(8*2)) | (2u<<(9*2));       // 10 = Alternate Function
    GPIOB->OTYPER |= (1u<<8) | (1u<<9);                // 1 = open-drain (mandatory for I2C)
    GPIOB->OSPEEDR|= (3u<<(8*2)) | (3u<<(9*2));        // 11 = very high speed
    GPIOB->PUPDR   = (GPIOB->PUPDR  & ~((3u<<(8*2)) | (3u<<(9*2))))
                   | (1u<<(8*2)) | (1u<<(9*2));       // 01 = pull-up (external Rp still required)
    GPIOB->AFR[1]  = (GPIOB->AFR[1] & ~((0xFu<<((8-8)*4)) | (0xFu<<((9-8)*4))))
                   | (4u<<((8-8)*4)) | (4u<<((9-8)*4)); // AF4, AFR[1]=AFRH for pins 8..15

    // 3) Enable the I2C1 peripheral clock.
    RCC->APB1ENR1 |= RCC_APB1ENR1_I2C1EN;
    (void)RCC->APB1ENR1;

    // 4) Program timing and features ONLY while PE = 0.
    I2C1->CR1     &= ~I2C_CR1_PE;                    // disable to configure / reset FSM
    I2C1->TIMINGR = 0x10320309;                      // 400 kHz @ 16 MHz kernel (RM0432)
    I2C1->CR1     &= ~I2C_CR1_ANFOFF;                // analog filter ON (recommended)
    I2C1->CR1     &= ~I2C_CR1_NOSTRETCH;             // master must allow clock stretching
    I2C1->CR1     |=  I2C_CR1_PE;                     // enable
}

#include "stm32l4r5xx.h"
#include <stdint.h>

// Build the CR2 "transaction descriptor" and fire START in one write.
static void i2c_cr2_start(I2C_TypeDef *i2c, uint8_t addr7,
                          uint8_t nbytes, int read, int autoend)
{
    uint32_t cr2 = (((uint32_t)addr7 << 1) & I2C_CR2_SADD)          // 7-bit addr in SADD[7:1]
                 | (((uint32_t)nbytes << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES)
                 | (read    ? I2C_CR2_RD_WRN  : 0u)
                 | (autoend ? I2C_CR2_AUTOEND : 0u)
                 | I2C_CR2_START;
    i2c->CR2 = cr2;   // writing whole CR2 also clears ADD10/RELOAD/etc. for a clean master frame
}

// Master WRITE n bytes. Returns 0 on success, -1 on NACK.
int i2c_write(I2C_TypeDef *i2c, uint8_t addr7, const uint8_t *buf, uint8_t n)
{
    while (i2c->ISR & I2C_ISR_BUSY) { }             // wait for a free bus
    i2c_cr2_start(i2c, addr7, n, 0, 1);            // write, AUTOEND

    for (uint8_t i = 0; i < n; i++) {
        while (!(i2c->ISR & (I2C_ISR_TXIS | I2C_ISR_NACKF))) { }
        if (i2c->ISR & I2C_ISR_NACKF) {            // slave did not ACK
            i2c->ICR = I2C_ICR_NACKCF;
            while (!(i2c->ISR & I2C_ISR_STOPF)) { }
            i2c->ICR = I2C_ICR_STOPCF;
            return -1;
        }
        i2c->TXDR = buf[i];
    }
    while (!(i2c->ISR & I2C_ISR_STOPF)) { }         // AUTOEND issued STOP
    i2c->ICR = I2C_ICR_STOPCF;
    return 0;
}

// Master READ n bytes. Returns 0 on success, -1 on address NACK.
int i2c_read(I2C_TypeDef *i2c, uint8_t addr7, uint8_t *buf, uint8_t n)
{
    while (i2c->ISR & I2C_ISR_BUSY) { }
    i2c_cr2_start(i2c, addr7, n, 1, 1);            // read, AUTOEND

    for (uint8_t i = 0; i < n; i++) {
        while (!(i2c->ISR & (I2C_ISR_RXNE | I2C_ISR_NACKF))) { }
        if (i2c->ISR & I2C_ISR_NACKF) {
            i2c->ICR = I2C_ICR_NACKCF;
            while (!(i2c->ISR & I2C_ISR_STOPF)) { }
            i2c->ICR = I2C_ICR_STOPCF;
            return -1;
        }
        buf[i] = (uint8_t)i2c->RXDR;
    }
    while (!(i2c->ISR & I2C_ISR_STOPF)) { }
    i2c->ICR = I2C_ICR_STOPCF;
    return 0;
}

// Write register pointer, then repeated-START and read n bytes (classic sensor read).
// Phase 1 uses AUTOEND=0 so the bus is held (TC) instead of STOP -> a real restart.
int i2c_read_reg(I2C_TypeDef *i2c, uint8_t addr7, uint8_t reg, uint8_t *buf, uint8_t n)
{
    while (i2c->ISR & I2C_ISR_BUSY) { }

    i2c_cr2_start(i2c, addr7, 1, 0, 0);            // write 1 byte, NO AUTOEND
    while (!(i2c->ISR & (I2C_ISR_TXIS | I2C_ISR_NACKF))) { }
    if (i2c->ISR & I2C_ISR_NACKF) { i2c->ICR = I2C_ICR_NACKCF; return -1; }
    i2c->TXDR = reg;
    while (!(i2c->ISR & I2C_ISR_TC)) { }            // transfer complete, bus still owned

    i2c_cr2_start(i2c, addr7, n, 1, 1);            // repeated START, read, AUTOEND
    for (uint8_t i = 0; i < n; i++) {
        while (!(i2c->ISR & I2C_ISR_RXNE)) { }
        buf[i] = (uint8_t)i2c->RXDR;
    }
    while (!(i2c->ISR & I2C_ISR_STOPF)) { }
    i2c->ICR = I2C_ICR_STOPCF;
    return 0;
}

// Example: read 6 bytes of accel data (reg 0x3B) from an MPU-6050 at 7-bit addr 0x68.
void demo(void)
{
    uint8_t accel[6];
    i2c_read_reg(I2C1, 0x68, 0x3B, accel, 6);
}

#include "stm32l4xx_hal.h"

I2C_HandleTypeDef hi2c1;

void MX_I2C1_Init(void)
{
    hi2c1.Instance             = I2C1;
    hi2c1.Init.Timing          = 0x10320309;              // 400 kHz @ 16 MHz I2CCLK (from CubeMX)
    hi2c1.Init.OwnAddress1     = 0;
    hi2c1.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
    hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
    hi2c1.Init.OwnAddress2     = 0;
    hi2c1.Init.OwnAddress2Masks= I2C_OA2_NOMASK;
    hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
    hi2c1.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;    // master: keep stretching enabled
    if (HAL_I2C_Init(&hi2c1) != HAL_OK) { Error_Handler(); }

    HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE);
    HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0);
}

// Select HSI16 as the I2C1 kernel clock (matches the 16 MHz Timing value above).
void I2C1_SelectHSI16(void)
{
    RCC_PeriphCLKInitTypeDef p = {0};
    p.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
    p.I2c1ClockSelection   = RCC_I2C1CLKSOURCE_HSI;
    if (HAL_RCCEx_PeriphCLKConfig(&p) != HAL_OK) { Error_Handler(); }
}

// HAL_I2C_MspInit is called by HAL_I2C_Init: enable clocks + configure the AF pins.
void HAL_I2C_MspInit(I2C_HandleTypeDef *h)
{
    if (h->Instance == I2C1) {
        __HAL_RCC_GPIOB_CLK_ENABLE();
        __HAL_RCC_I2C1_CLK_ENABLE();
        GPIO_InitTypeDef g = {0};
        g.Pin       = GPIO_PIN_8 | GPIO_PIN_9;            // PB8=SCL, PB9=SDA
        g.Mode      = GPIO_MODE_AF_OD;                    // alternate function, open-drain
        g.Pull      = GPIO_NOPULL;                        // external pull-ups on the board
        g.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
        g.Alternate = GPIO_AF4_I2C1;
        HAL_GPIO_Init(GPIOB, &g);
    }
}

void demo_hal(void)
{
    uint8_t cfg[2] = { 0x6B, 0x00 };                      // MPU-6050: PWR_MGMT_1 = 0 (wake)
    uint8_t accel[6];
    // NOTE the <<1 : HAL wants the 8-bit address. 7-bit 0x68 -> 0xD0.
    HAL_I2C_Master_Transmit(&hi2c1, (0x68 << 1), cfg, 2, HAL_MAX_DELAY);
    HAL_I2C_Mem_Read(&hi2c1, (0x68 << 1), 0x3B,
                     I2C_MEMADD_SIZE_8BIT, accel, 6, HAL_MAX_DELAY);
}

#include "stm32l4r5xx.h"

// Transmit 'n' bytes from 'buf' to a 7-bit slave using DMA1 Channel 1 + DMAMUX.
void i2c1_dma_write(uint8_t addr7, const uint8_t *buf, uint8_t n)
{
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN;

    // Route DMAMUX1 channel 0 (drives DMA1_Channel1) to I2C1_TX request line 17.
    DMAMUX1_Channel0->CCR = 17u;                    // DMAMUX_CxCR.DMAREQ_ID = 17

    DMA1_Channel1->CCR &= ~DMA_CCR_EN;              // disable while configuring
    DMA1_Channel1->CPAR  = (uint32_t)&I2C1->TXDR;   // peripheral = TXDR
    DMA1_Channel1->CMAR  = (uint32_t)buf;           // memory = source buffer
    DMA1_Channel1->CNDTR = n;
    DMA1_Channel1->CCR   = DMA_CCR_MINC             // increment memory
                         | DMA_CCR_DIR              // 1 = read-from-memory (mem -> periph)
                         | DMA_CCR_EN;              // byte-wide (PSIZE=MSIZE=00) is fine for I2C

    I2C1->CR1 |= I2C_CR1_TXDMAEN;                   // TXIS now triggers a DMA request

    // Kick the frame exactly like the polled case: addr, NBYTES=n, write, AUTOEND, START.
    I2C1->CR2 = (((uint32_t)addr7 << 1) & I2C_CR2_SADD)
              | (((uint32_t)n << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES)
              | I2C_CR2_AUTOEND | I2C_CR2_START;

    while (!(I2C1->ISR & I2C_ISR_STOPF)) { }        // DMA feeds TXDR; STOP when NBYTES done
    I2C1->ICR = I2C_ICR_STOPCF;
    I2C1->CR1 &= ~I2C_CR1_TXDMAEN;
    DMA1_Channel1->CCR &= ~DMA_CCR_EN;
}

DMA_HandleTypeDef hdma_i2c1_tx;

void I2C1_DMA_Init(void)
{
    __HAL_RCC_DMA1_CLK_ENABLE();
    __HAL_RCC_DMAMUX1_CLK_ENABLE();

    hdma_i2c1_tx.Instance                 = DMA1_Channel1;
    hdma_i2c1_tx.Init.Request             = DMA_REQUEST_I2C1_TX;   // == 17
    hdma_i2c1_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
    hdma_i2c1_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
    hdma_i2c1_tx.Init.MemInc              = DMA_MINC_ENABLE;
    hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_i2c1_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
    hdma_i2c1_tx.Init.Mode                = DMA_NORMAL;
    hdma_i2c1_tx.Init.Priority            = DMA_PRIORITY_HIGH;
    HAL_DMA_Init(&hdma_i2c1_tx);
    __HAL_LINKDMA(&hi2c1, hdmatx, hdma_i2c1_tx);

    HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);   // + call HAL_DMA_IRQHandler(&hdma_i2c1_tx) in it
    HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);         // + call HAL_I2C_EV_IRQHandler(&hi2c1)
}

void demo_dma(void)
{
    static uint8_t buf[32];
    HAL_I2C_Master_Transmit_DMA(&hi2c1, (0x50 << 1), buf, sizeof buf);
    // completion signalled by HAL_I2C_MasterTxCpltCallback()
}