STM32L4R5 Timers
PWM, input capture, encoder & low-power.

#include "stm32l4r5xx.h"   /* CMSIS device header (via stm32l4xx.h) */

void TIM3_timebase_1kHz(void)
{
    /* 1. Clock the timer, then read-back so the enable settles */
    RCC->APB1ENR1 |= RCC_APB1ENR1_TIM3EN;
    (void)RCC->APB1ENR1;

    /* 2. CK_CNT = 120 MHz / (119+1) = 1 MHz */
    TIM3->PSC = 120 - 1;

    /* 3. UEV = 1 MHz / (999+1) = 1 kHz */
    TIM3->ARR = 1000 - 1;

    /* 4. Buffer ARR so mid-flight changes are glitch-free */
    TIM3->CR1 |= TIM_CR1_ARPE;

    /* 5. Force an update NOW so PSC/ARR shadow registers load
     *    before the counter starts (otherwise first period is wrong) */
    TIM3->EGR  = TIM_EGR_UG;
    TIM3->SR  &= ~TIM_SR_UIF;          /* clear the flag UG just set */

    /* 6. Enable update interrupt and start counting */
    TIM3->DIER |= TIM_DIER_UIE;
    TIM3->CR1  |= TIM_CR1_CEN;

    NVIC_SetPriority(TIM3_IRQn, 5);
    NVIC_EnableIRQ(TIM3_IRQn);
}

volatile uint32_t g_ticks;
void TIM3_IRQHandler(void)
{
    if (TIM3->SR & TIM_SR_UIF) {
        TIM3->SR = ~TIM_SR_UIF;        /* rc_w0: write 0 to clear */
        g_ticks++;
    }
}

#include "stm32l4r5xx.h"

void TIM3_CH1_pwm_20kHz_25pct(void)
{
    /* ---- GPIO: PC6 as AF2 (TIM3_CH1) ---- */
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOCEN;
    (void)RCC->AHB2ENR;

    GPIOC->MODER  &= ~GPIO_MODER_MODE6;         /* clear pin 6 mode  */
    GPIOC->MODER  |=  (0x2u << GPIO_MODER_MODE6_Pos); /* 10 = alt func */
    GPIOC->OSPEEDR |= (0x3u << GPIO_OSPEEDR_OSPEED6_Pos); /* high speed */
    GPIOC->AFR[0] &= ~GPIO_AFRL_AFSEL6;
    GPIOC->AFR[0] |=  (2u << GPIO_AFRL_AFSEL6_Pos);  /* AF2 = TIM3     */

    /* ---- Timer time-base ---- */
    RCC->APB1ENR1 |= RCC_APB1ENR1_TIM3EN;
    (void)RCC->APB1ENR1;

    TIM3->PSC = 1 - 1;                 /* no prescale, CK_CNT = 120 MHz */
    TIM3->ARR = 6000 - 1;             /* 120e6/6000 = 20 kHz            */
    TIM3->CCR1 = 1500;               /* 1500/6000 = 25 % duty          */

    /* ---- Channel 1 as PWM mode 1, preload on ---- */
    TIM3->CCMR1 &= ~TIM_CCMR1_CC1S;   /* CC1S=00 → output              */
    TIM3->CCMR1 &= ~TIM_CCMR1_OC1M;
    TIM3->CCMR1 |=  (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1); /* 0110      */
    TIM3->CCMR1 |=  TIM_CCMR1_OC1PE;  /* buffer CCR1                    */

    TIM3->CCER  &= ~TIM_CCER_CC1P;    /* active-high                    */
    TIM3->CCER  |=  TIM_CCER_CC1E;    /* enable OC1 pin                 */

    TIM3->CR1   |=  TIM_CR1_ARPE;     /* buffer ARR                     */
    TIM3->EGR    =  TIM_EGR_UG;       /* load shadows                   */
    TIM3->CR1   |=  TIM_CR1_CEN;      /* GO                             */
}

/* Change duty at runtime (safe because CCR1 is buffered): */
static inline void TIM3_CH1_set_duty(uint16_t permille)  /* 0..1000 */
{
    TIM3->CCR1 = (uint16_t)(((uint32_t)(TIM3->ARR + 1) * permille) / 1000u);
}

#include "stm32l4xx_hal.h"

TIM_HandleTypeDef htim3;

void TIM3_CH1_pwm_hal(void)
{
    __HAL_RCC_GPIOC_CLK_ENABLE();
    __HAL_RCC_TIM3_CLK_ENABLE();

    GPIO_InitTypeDef g = {0};
    g.Pin       = GPIO_PIN_6;
    g.Mode      = GPIO_MODE_AF_PP;
    g.Pull      = GPIO_NOPULL;
    g.Speed     = GPIO_SPEED_FREQ_HIGH;
    g.Alternate = GPIO_AF2_TIM3;
    HAL_GPIO_Init(GPIOC, &g);

    htim3.Instance           = TIM3;
    htim3.Init.Prescaler     = 1 - 1;
    htim3.Init.CounterMode   = TIM_COUNTERMODE_UP;
    htim3.Init.Period        = 6000 - 1;          /* ARR → 20 kHz */
    htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
    htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
    HAL_TIM_PWM_Init(&htim3);

    TIM_OC_InitTypeDef oc = {0};
    oc.OCMode     = TIM_OCMODE_PWM1;
    oc.Pulse      = 1500;                          /* 25 % duty */
    oc.OCPolarity = TIM_OCPOLARITY_HIGH;
    oc.OCFastMode = TIM_OCFAST_DISABLE;
    HAL_TIM_PWM_ConfigChannel(&htim3, &oc, TIM_CHANNEL_1);

    HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
}

/* Runtime duty update: */
/*   __HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_1, new_ccr); */

#include "stm32l4r5xx.h"

/* PA8 = TIM1_CH1 (AF1), PB13 = TIM1_CH1N (AF1) */
void TIM1_complementary_pwm(void)
{
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN;
    RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
    (void)RCC->APB2ENR;

    /* PA8 → AF1 */
    GPIOA->MODER  &= ~GPIO_MODER_MODE8;
    GPIOA->MODER  |=  (0x2u << GPIO_MODER_MODE8_Pos);
    GPIOA->AFR[1] &= ~GPIO_AFRH_AFSEL8;
    GPIOA->AFR[1] |=  (1u << GPIO_AFRH_AFSEL8_Pos);
    /* PB13 → AF1 */
    GPIOB->MODER  &= ~GPIO_MODER_MODE13;
    GPIOB->MODER  |=  (0x2u << GPIO_MODER_MODE13_Pos);
    GPIOB->AFR[1] &= ~GPIO_AFRH_AFSEL13;
    GPIOB->AFR[1] |=  (1u << GPIO_AFRH_AFSEL13_Pos);

    /* 120 MHz / 6000 = 20 kHz, 50 % duty */
    TIM1->PSC  = 0;
    TIM1->ARR  = 6000 - 1;
    TIM1->CCR1 = 3000;

    TIM1->CCMR1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_OC1M);
    TIM1->CCMR1 |=  (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /* PWM1 */
                 |   TIM_CCMR1_OC1PE;

    /* Enable BOTH OC1 and OC1N, both active-high */
    TIM1->CCER  |= TIM_CCER_CC1E | TIM_CCER_CC1NE;

    /* Dead-time = 60 × t_DTS ≈ 500 ns; MOE must be set on advanced timers */
    TIM1->CR1  &= ~TIM_CR1_CKD;                 /* CKD=00 → t_DTS = 8.33 ns */
    TIM1->BDTR  = (60u << TIM_BDTR_DTG_Pos)     /* DTG field                */
                | TIM_BDTR_OSSR                 /* drive off-state in run   */
                | TIM_BDTR_MOE;                 /* MAIN OUTPUT ENABLE       */

    TIM1->CR1  |= TIM_CR1_ARPE;
    TIM1->EGR   = TIM_EGR_UG;
    TIM1->CR1  |= TIM_CR1_CEN;
}

TIM_HandleTypeDef htim1;

void TIM1_complementary_hal(void)
{
    /* ...clock + PA8/PB13 GPIO AF1 init as above... */
    htim1.Instance = TIM1;
    htim1.Init.Prescaler   = 0;
    htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
    htim1.Init.Period      = 6000 - 1;
    htim1.Init.RepetitionCounter = 0;
    htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
    HAL_TIM_PWM_Init(&htim1);

    TIM_OC_InitTypeDef oc = {0};
    oc.OCMode      = TIM_OCMODE_PWM1;
    oc.Pulse       = 3000;                    /* 50 % */
    oc.OCPolarity  = TIM_OCPOLARITY_HIGH;
    oc.OCNPolarity = TIM_OCNPOLARITY_HIGH;
    oc.OCIdleState = TIM_OCIDLESTATE_RESET;
    oc.OCNIdleState= TIM_OCNIDLESTATE_RESET;
    HAL_TIM_PWM_ConfigChannel(&htim1, &oc, TIM_CHANNEL_1);

    TIM_BreakDeadTimeConfigTypeDef bd = {0};
    bd.OffStateRunMode  = TIM_OSSR_ENABLE;
    bd.OffStateIDLEMode = TIM_OSSI_DISABLE;
    bd.LockLevel        = TIM_LOCKLEVEL_OFF;
    bd.DeadTime         = 60;                 /* raw DTG value */
    bd.BreakState       = TIM_BREAK_DISABLE;
    bd.AutomaticOutput  = TIM_AUTOMATICOUTPUT_DISABLE;
    HAL_TIMEx_ConfigBreakDeadTime(&htim1, &bd);

    HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);     /* OC1  */
    HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_1);  /* OC1N */
}

#include "stm32l4r5xx.h"

volatile uint32_t g_period_ticks;    /* CK_CNT ticks between rising edges */
volatile uint8_t  g_valid;

void TIM2_CH1_capture_init(void)
{
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
    RCC->APB1ENR1 |= RCC_APB1ENR1_TIM2EN;
    (void)RCC->APB1ENR1;

    /* PA0 → AF1 (TIM2_CH1) input */
    GPIOA->MODER  &= ~GPIO_MODER_MODE0;
    GPIOA->MODER  |=  (0x2u << GPIO_MODER_MODE0_Pos);
    GPIOA->AFR[0] &= ~GPIO_AFRL_AFSEL0;
    GPIOA->AFR[0] |=  (1u << GPIO_AFRL_AFSEL0_Pos);

    /* Free-running 1 MHz time base (PSC=119), full 32-bit range */
    TIM2->PSC = 120 - 1;
    TIM2->ARR = 0xFFFFFFFFu;

    /* CH1 = input, mapped to TI1 (CC1S=01), light filter (ICxF=0011) */
    TIM2->CCMR1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F);
    TIM2->CCMR1 |=  (1u << TIM_CCMR1_CC1S_Pos)
                 |  (3u << TIM_CCMR1_IC1F_Pos);

    /* Rising edge (CC1P=0, CC1NP=0), enable capture */
    TIM2->CCER  &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
    TIM2->CCER  |=  TIM_CCER_CC1E;

    TIM2->DIER  |=  TIM_DIER_CC1IE;      /* capture interrupt */
    TIM2->EGR    =  TIM_EGR_UG;
    TIM2->CR1   |=  TIM_CR1_CEN;

    NVIC_SetPriority(TIM2_IRQn, 5);
    NVIC_EnableIRQ(TIM2_IRQn);
}

void TIM2_IRQHandler(void)
{
    static uint32_t last;
    if (TIM2->SR & TIM_SR_CC1IF) {
        uint32_t now = TIM2->CCR1;       /* reading CCR1 clears CC1IF */
        g_period_ticks = now - last;    /* 32-bit wrap is automatic   */
        last = now;
        g_valid = 1;
        /* if (TIM2->SR & TIM_SR_CC1OF) { overcapture — ISR too slow } */
    }
}
/* f_signal[Hz] = 1e6 / g_period_ticks   (because CK_CNT = 1 MHz) */

#include "stm32l4r5xx.h"

void TIM3_encoder_init(uint16_t counts_per_rev_x4)
{
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN;
    RCC->APB1ENR1 |= RCC_APB1ENR1_TIM3EN;
    (void)RCC->APB1ENR1;

    /* PA6, PA7 → AF2 inputs */
    GPIOA->MODER  &= ~(GPIO_MODER_MODE6 | GPIO_MODER_MODE7);
    GPIOA->MODER  |=  (0x2u << GPIO_MODER_MODE6_Pos)
                  |   (0x2u << GPIO_MODER_MODE7_Pos);
    GPIOA->AFR[0] &= ~(GPIO_AFRL_AFSEL6 | GPIO_AFRL_AFSEL7);
    GPIOA->AFR[0] |=  (2u << GPIO_AFRL_AFSEL6_Pos)
                  |   (2u << GPIO_AFRL_AFSEL7_Pos);

    /* CH1=TI1, CH2=TI2, both direct inputs, with input filters */
    TIM3->CCMR1 = (1u << TIM_CCMR1_CC1S_Pos)   /* CC1S=01 → IC1 on TI1 */
                | (1u << TIM_CCMR1_CC2S_Pos)   /* CC2S=01 → IC2 on TI2 */
                | (5u << TIM_CCMR1_IC1F_Pos)   /* filter               */
                | (5u << TIM_CCMR1_IC2F_Pos);

    /* Non-inverted; CCxP selects the counting direction reference */
    TIM3->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP
                  | TIM_CCER_CC2P | TIM_CCER_CC2NP);
    TIM3->CCER |=  TIM_CCER_CC1E | TIM_CCER_CC2E;

    /* Encoder mode 3 (×4): SMS = 011 */
    TIM3->SMCR &= ~TIM_SMCR_SMS;
    TIM3->SMCR |=  (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0);

    /* Wrap at one mechanical revolution so CNT reads absolute position */
    TIM3->ARR = counts_per_rev_x4 - 1;
    TIM3->CNT = 0;
    TIM3->CR1 |= TIM_CR1_CEN;
}

/* Read anywhere, no IRQ needed: */
static inline uint16_t enc_position(void) { return (uint16_t)TIM3->CNT; }
static inline int enc_direction(void) {                 /* 1=down, 0=up */
    return (TIM3->CR1 & TIM_CR1_DIR) ? 1 : 0;
}

#include "stm32l4r5xx.h"

/* PB8 = TIM16_CH1 (AF14) */
void TIM16_one_pulse(void)
{
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN;
    RCC->APB2ENR |= RCC_APB2ENR_TIM16EN;
    (void)RCC->APB2ENR;

    GPIOB->MODER  &= ~GPIO_MODER_MODE8;
    GPIOB->MODER  |=  (0x2u << GPIO_MODER_MODE8_Pos);
    GPIOB->AFR[1] &= ~GPIO_AFRH_AFSEL8;
    GPIOB->AFR[1] |=  (14u << GPIO_AFRH_AFSEL8_Pos);

    TIM16->PSC  = 120 - 1;      /* 1 MHz  */
    TIM16->ARR  = 15  - 1;      /* total 15 us */
    TIM16->CCR1 = 10;           /* 10 us delay, then 5 us pulse */

    /* PWM mode 2 (0111) so output goes high only after CCR1 */
    TIM16->CCMR1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_OC1M);
    TIM16->CCMR1 |=  (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
                  |   TIM_CCMR1_OC1PE;
    TIM16->CCER  |= TIM_CCER_CC1E;

    /* TIM16 is a break-capable timer → MOE required */
    TIM16->BDTR  |= TIM_BDTR_MOE;

    TIM16->CR1   |= TIM_CR1_OPM;    /* single shot */
    TIM16->EGR    = TIM_EGR_UG;
}

/* Fire one pulse (software trigger). For a hardware trigger, program
 * SMCR: SMS=110 (trigger) + TS= instead of setting CEN here. */
void TIM16_fire(void) { TIM16->CR1 |= TIM_CR1_CEN; }

#include "stm32l4r5xx.h"

void LPTIM1_pwm_from_LSE(void)
{
    /* Assume LSE already started (RCC_BDCR.LSEON, LSERDY). */
    RCC->CCIPR = (RCC->CCIPR & ~RCC_CCIPR_LPTIM1SEL)
               | (0x3u << RCC_CCIPR_LPTIM1SEL_Pos);   /* 11 = LSE */
    RCC->APB1ENR1 |= RCC_APB1ENR1_LPTIM1EN;
    (void)RCC->APB1ENR1;

    /* Config MUST be written while DISABLED */
    LPTIM1->CR = 0;
    LPTIM1->CFGR = (0u << LPTIM_CFGR_PRESC_Pos);  /* PRESC=÷1, internal clk */
    /* WAVE=0, WAVPOL=0 → standard PWM, active per compare */

    /* Enable the peripheral BEFORE loading ARR/CMP */
    LPTIM1->CR |= LPTIM_CR_ENABLE;

    /* Write period, wait for ARROK, then compare, wait for CMPOK */
    LPTIM1->ARR = 256 - 1;
    while (!(LPTIM1->ISR & LPTIM_ISR_ARROK)) { }
    LPTIM1->ICR = LPTIM_ICR_ARROKCF;

    LPTIM1->CMP = 128;                    /* ~50 % */
    while (!(LPTIM1->ISR & LPTIM_ISR_CMPOK)) { }
    LPTIM1->ICR = LPTIM_ICR_CMPOKCF;

    /* Start continuous counting → PWM appears on LPTIM1_OUT */
    LPTIM1->CR |= LPTIM_CR_CNTSTRT;
}