Interrupts on the STM32L4R5
NVIC, EXTI & ISR handling

/* Order matters: set priority BEFORE enabling, so the first
 * interrupt is already at the priority you intended.          */
NVIC_SetPriority(EXTI0_IRQn, 5);   /* 0 = highest, 15 = lowest */
NVIC_EnableIRQ(EXTI0_IRQn);        /* unmask in the NVIC       */

/* Mirror operations */
NVIC_DisableIRQ(EXTI0_IRQn);
NVIC_ClearPendingIRQ(EXTI0_IRQn);  /* clears the NVIC latch, NOT EXTI->PR1 */
uint32_t p = NVIC_GetPriority(EXTI0_IRQn);

#define IRQ  EXTI0_IRQn                       /* = 6 */

/* Enable: 32 IRQs per 32-bit word */
NVIC->ISER[IRQ >> 5] = (1u << (IRQ & 0x1F));   /* ISER[0], bit 6 */

/* Priority: one 8-bit IPR byte per IRQ; STM32 uses the TOP 4 bits,
 * so the value is left-shifted by (8 - __NVIC_PRIO_BITS) = 4.        */
NVIC->IPR[IRQ] = (uint8_t)(5u << (8 - __NVIC_PRIO_BITS)); /* 5<<4 = 0x50 */

/* Disable / clear-pending use the mirror arrays */
NVIC->ICER[IRQ >> 5] = (1u << (IRQ & 0x1F));   /* Clear-Enable  */
NVIC->ICPR[IRQ >> 5] = (1u << (IRQ & 0x1F));   /* Clear-Pending */

/* Raw CMSIS: choose 2 group bits + 2 sub bits (PRIGROUP = 5) */
NVIC_SetPriorityGrouping(5u);
uint32_t prio = NVIC_EncodePriority(NVIC_GetPriorityGrouping(),
                                    2,   /* pre-emption level 0..3 */
                                    1);  /* sub-priority      0..3 */
NVIC_SetPriority(EXTI0_IRQn, prio);

/* HAL: HAL_Init() already forced group 4, so 'sub' does nothing */
HAL_NVIC_SetPriority(EXTI0_IRQn, 5, 0);  /* (IRQn, preempt, sub) */
HAL_NVIC_EnableIRQ(EXTI0_IRQn);

g_pfnVectors:
  .word  _estack
  .word  Reset_Handler
  /* ... core exceptions ... */
  .word  EXTI0_IRQHandler        /* IRQ  6 */
  .word  EXTI1_IRQHandler        /* IRQ  7 */
  /* ... */
  .word  EXTI9_5_IRQHandler      /* IRQ 23 */
  /* ... */
  .word  EXTI15_10_IRQHandler    /* IRQ 40 */

  /* Each handler is a WEAK alias of Default_Handler: */
  .weak      EXTI0_IRQHandler
  .thumb_set EXTI0_IRQHandler, Default_Handler

#include "stm32l4r5xx.h"   /* CMSIS: EXTI, GPIOx, RCC, SYSCFG, NVIC_*, IRQn */

/* Shared with main loop -> MUST be volatile or the compiler may cache it */
volatile uint32_t g_presses = 0;

/* Vector-table symbol: name MUST match startup_stm32l4r5xx.s EXACTLY */
void EXTI0_IRQHandler(void)
{
    if (EXTI->PR1 & EXTI_PR1_PIF0) {   /* did line 0 fire?         */
        EXTI->PR1 = EXTI_PR1_PIF0;     /* clear pending: write 1   */
        GPIOC->ODR ^= GPIO_ODR_OD7;    /* toggle LD1               */
        g_presses++;
    }
}

int main(void)
{
    /* 1) Clocks: GPIOA + GPIOC on AHB2, SYSCFG on APB2 */
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOCEN;
    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;   /* WITHOUT this, EXTICR stays PA */
    (void)RCC->APB2ENR;                      /* read-back: let the clock settle */

    /* 2) PA0 = input (MODER 00) with pull-up (PUPDR 01) */
    GPIOA->MODER &= ~GPIO_MODER_MODE0;
    GPIOA->PUPDR = (GPIOA->PUPDR & ~GPIO_PUPDR_PUPD0)
                 | (1u << GPIO_PUPDR_PUPD0_Pos);

    /* 3) PC7 = general-purpose output (MODER 01), push-pull default */
    GPIOC->MODER = (GPIOC->MODER & ~GPIO_MODER_MODE7)
                 | (1u << GPIO_MODER_MODE7_Pos);

    /* 4) Route EXTI0 to port A (EXTICR1 field EXTI0 = 0x0 = PA) */
    SYSCFG->EXTICR[0] &= ~SYSCFG_EXTICR1_EXTI0;

    /* 5) EXTI line 0: falling edge only, clear stale, then unmask */
    EXTI->RTSR1 &= ~EXTI_RTSR1_RT0;   /* no rising edge   */
    EXTI->FTSR1 |=  EXTI_FTSR1_FT0;   /* falling edge     */
    EXTI->PR1    =  EXTI_PR1_PIF0;    /* clear stale flag BEFORE unmask */
    EXTI->IMR1  |=  EXTI_IMR1_IM0;    /* unmask -> reaches NVIC */

    /* 6) NVIC: priority (0..15) THEN enable */
    NVIC_SetPriority(EXTI0_IRQn, 5);
    NVIC_EnableIRQ(EXTI0_IRQn);

    while (1) {
        __WFI();   /* sleep until any interrupt wakes the core */
    }
}

void MX_GPIO_Init(void)
{
    GPIO_InitTypeDef g = {0};

    __HAL_RCC_GPIOA_CLK_ENABLE();
    __HAL_RCC_GPIOC_CLK_ENABLE();
    __HAL_RCC_SYSCFG_CLK_ENABLE();   /* required for EXTI line muxing */

    /* PA0 -> external interrupt, falling edge, pull-up */
    g.Pin  = GPIO_PIN_0;
    g.Mode = GPIO_MODE_IT_FALLING;   /* IT = interrupt (EVT = event, no ISR) */
    g.Pull = GPIO_PULLUP;
    HAL_GPIO_Init(GPIOA, &g);

    /* PC7 -> push-pull output (LED) */
    g.Pin   = GPIO_PIN_7;
    g.Mode  = GPIO_MODE_OUTPUT_PP;
    g.Pull  = GPIO_NOPULL;
    g.Speed = GPIO_SPEED_FREQ_LOW;
    HAL_GPIO_Init(GPIOC, &g);

    /* NVIC (HAL_Init selected NVIC_PRIORITYGROUP_4 -> sub-priority ignored) */
    HAL_NVIC_SetPriority(EXTI0_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(EXTI0_IRQn);
}

void EXTI0_IRQHandler(void)
{
    /* Clears EXTI->PR1 for pin 0 AND calls HAL_GPIO_EXTI_Callback() */
    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
}

void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
    if (GPIO_Pin == GPIO_PIN_0) {
        HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_7);   /* toggle LD1 */
    }
}

/* Mux EXTI13 -> port C. Line 13 lives in EXTICR[3], field bits [7:4]. */
SYSCFG->EXTICR[3] = (SYSCFG->EXTICR[3] & ~SYSCFG_EXTICR4_EXTI13)
                 | SYSCFG_EXTICR4_EXTI13_PC;   /* 0x20 selects PC */
EXTI->FTSR1 |= EXTI_FTSR1_FT13;
EXTI->PR1   =  EXTI_PR1_PIF13;                  /* clear stale */
EXTI->IMR1  |= EXTI_IMR1_IM13;
NVIC_SetPriority(EXTI15_10_IRQn, 6);
NVIC_EnableIRQ(EXTI15_10_IRQn);

/* One handler serves lines 10..15 -> you MUST check which line fired */
void EXTI15_10_IRQHandler(void)
{
    if (EXTI->PR1 & EXTI_PR1_PIF13) {
        EXTI->PR1 = EXTI_PR1_PIF13;   /* clear ONLY the line handled */
        /* ... service the button ... */
    }
    /* other lines (10,11,12,14,15) would each test their own PIF bit */
}

EXTI->SWIER1 = EXTI_SWIER1_SWI0;   /* sets PR1 bit 0 -> runs EXTI0_IRQHandler */