SWD, SWO Trace & RTT
printf-Debug over the Probe

/* SWO printf for STM32L4R5 (Cortex-M4F).  No HAL required.
 * Emits ITM stimulus-port-0 bytes on PB3 / TRACESWO, async NRZ (UART) encoding.
 * Call SWO_Init(SystemCoreClock, 2000000) once after the clock tree is final. */
#include <stdint.h>
#include "stm32l4xx.h"   /* CMSIS device header: defines ITM, TPI, DWT, CoreDebug, DBGMCU, GPIOB, RCC */

void SWO_Init(uint32_t hclk_hz, uint32_t swo_baud)
{
    /* --- 1. Route PB3 to TRACESWO (AF0), very-high speed --------------- */
    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN;              /* clock GPIOB */
    GPIOB->MODER   = (GPIOB->MODER   & ~(3u << (3*2))) | (2u << (3*2)); /* PB3 = AF mode */
    GPIOB->OSPEEDR |=  (3u << (3*2));                  /* very-high output speed */
    GPIOB->AFR[0]  = (GPIOB->AFR[0] & ~(0xFu << (3*4))) | (0u << (3*4)); /* AF0 = TRACESWO */

    /* --- 2. STM32 debug mux: async trace, drive the trace IO --------- */
    DBGMCU->CR &= ~DBGMCU_CR_TRACE_MODE;              /* TRACE_MODE = 00 -> async SWO */
    DBGMCU->CR |=  DBGMCU_CR_TRACE_IOEN;              /* enable trace pin(s) */

    /* --- 3. Master trace enable ------------------------------------- */
    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;   /* DEMCR bit 24 */

    /* --- 4. TPIU: NRZ encoding, prescaler, formatter OFF ------------ */
    TPI->ACPR = (hclk_hz / swo_baud) - 1u;            /* SWO_baud = HCLK/(ACPR+1) */
    TPI->SPPR = 2u;                                   /* 2 = NRZ/UART, 1 = Manchester */
    TPI->FFCR = 0x100u;                               /* formatter off (single ITM source) */

    /* --- 5. ITM: unlock, enable, open stimulus port 0 --------------- */
    ITM->LAR = 0xC5ACCE55u;                           /* unlock ITM registers */
    ITM->TCR = ITM_TCR_ITMENA_Msk                     /* enable ITM */
             | ITM_TCR_SYNCENA_Msk                   /* sync packets */
             | ITM_TCR_TSENA_Msk                     /* local timestamps */
             | (1u << ITM_TCR_TraceBusID_Pos);       /* ATB ID = 1 */
    ITM->TPR = 0x00000001u;                           /* allow unpriv. access to port 0 */
    ITM->TER = 0x00000001u;                           /* enable stimulus port 0 */
}

/* Blocking single-char write. Spins only while the FIFO is full AND a
 * debugger is draining it; if no probe is attached the port stays "ready"
 * because writes are simply dropped by hardware. */
void SWO_PutChar(uint8_t c)
{
    if ((ITM->TCR & ITM_TCR_ITMENA_Msk) == 0u) return;      /* ITM off */
    if ((ITM->TER & 1u) == 0u) return;                       /* port 0 disabled */
    while (ITM->PORT[0].u32 == 0u) { /* wait for FIFO ready */ }
    ITM->PORT[0].u8 = c;                                   /* 8-bit write = 1 byte packet */
}

#include "main.h"

void SWO_Init_HAL(uint32_t hclk_hz, uint32_t swo_baud)
{
    __HAL_RCC_GPIOB_CLK_ENABLE();
    GPIO_InitTypeDef g = {0};
    g.Pin       = GPIO_PIN_3;
    g.Mode      = GPIO_MODE_AF_PP;
    g.Pull      = GPIO_NOPULL;
    g.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
    g.Alternate = GPIO_AF0_TRACE;               /* PB3 -> TRACESWO */
    HAL_GPIO_Init(GPIOB, &g);

    DBGMCU->CR &= ~DBGMCU_CR_TRACE_MODE;
    DBGMCU->CR |=  DBGMCU_CR_TRACE_IOEN;
    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;

    TPI->ACPR = (hclk_hz / swo_baud) - 1u;
    TPI->SPPR = 2u;
    TPI->FFCR = 0x100u;
    ITM->LAR  = 0xC5ACCE55u;
    ITM->TCR  = ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk |
               ITM_TCR_TSENA_Msk   | (1u << ITM_TCR_TraceBusID_Pos);
    ITM->TPR  = 1u;
    ITM->TER  = 1u;
}

#include <unistd.h>
#include "stm32l4xx.h"

/* newlib syscall stub; STDOUT (fd 1) and STDERR (fd 2) go to SWO */
int _write(int fd, char *buf, int len)
{
    (void)fd;
    for (int i = 0; i < len; i++)
        ITM_SendChar((uint8_t)buf[i]);      /* CMSIS helper */
    return len;
}

/* Usage in main():
 *   SWO_Init(SystemCoreClock, 2000000);
 *   setvbuf(stdout, NULL, _IONBF, 0);    // no buffering -> lines appear live
 *   printf("boot ok, HCLK=%lu\r\n", SystemCoreClock);
 */

# Run:  openocd -f interface/stlink.cfg -f target/stm32l4x.cfg -f openocd-swo.cfg
init

# protocol uart = async NRZ; traceclk MUST equal the running HCLK (80 MHz here)
# pin-freq = SWO line rate you programmed into TPIU_ACPR (2 MHz here)
# -output can be:  filename | :port (TCP) | - (Tcl) | external
stm32l4x.tpiu configure -protocol uart -traceclk 80000000 \
    -pin-freq 2000000 -output /tmp/swo.fifo -formatter 0
stm32l4x.tpiu enable

itm ports off                      # mask all first
itm port 0 on                       # enable only stimulus 0

reset run

# itmdump from the Rust 'itm' crate:  cargo install itm --features cli
# -f/--file: file OR named pipe   -F/--follow: tail -f   -s/--stimulus: port (default 0)

mkfifo /tmp/swo.fifo                # create the pipe BEFORE starting OpenOCD
itmdump -f /tmp/swo.fifo -F -s 0   # prints your printf() text live

# Windows / no-FIFO alternative: let OpenOCD write a real file, then tail it
#   stm32l4x.tpiu configure ... -output swo.log ...
itmdump -f swo.log -F

# J-Link exports SWO on TCP 2332 (start JLinkGDBServer or JLinkExe first).
# orbcat: -s server:port  -c CHANNEL,FORMAT   (%c = raw char)
orbcat -s localhost:2332 -c 0,"%c"

# Statistical PC profiler over SWO — needs the ELF for symbol names
orbtop -s localhost:2332 -e build/firmware.elf

# Or run the mux once and attach many clients to it:
orbuculum -s localhost:2332          # daemon; then orbcat/orbtop connect to it

# The clock value MUST equal the running HCLK. Check exact flag with: st-trace --help
st-trace --clock=80000000        # reads stimulus port 0, prints to stdout

# ST-LINK GDB server route: it opens a raw SWO TCP port you can pipe to itmdump
nc localhost 3344 | itmdump -f /dev/stdin -F

#include "SEGGER_RTT.h"
#include "stm32l4xx.h"

int main(void)
{
    /* No clocks, no pins, no ITM — RTT rides the SWD link the probe already owns */
    SEGGER_RTT_Init();

    /* Default up-channel 0 is BLOCK-if-full; switch to NO-BLOCK for real-time safety
     * so logging never stalls the CPU when no debugger is draining the buffer. */
    SEGGER_RTT_ConfigUpBuffer(0, "Terminal", NULL, 0,
                              SEGGER_RTT_MODE_NO_BLOCK_SKIP);

    uint32_t n = 0;
    while (1) {
        SEGGER_RTT_printf(0, "tick %u  HCLK=%u\r\n",
                          (unsigned)n++, (unsigned)SystemCoreClock);

        /* Optional: read a byte the host typed into down-channel 0 */
        if (SEGGER_RTT_HasKey()) {
            int key = SEGGER_RTT_GetKey();
            SEGGER_RTT_printf(0, "got key: %c\r\n", key);
        }
        HAL_Delay(250);
    }
}

# openocd -f interface/stlink.cfg -f target/stm32l4x.cfg -f openocd-rtt.cfg
init
reset run

# Search 0x20000000..+2048 for a control block named "SEGGER RTT".
# If you pinned the address, pass that exact value as the first arg.
rtt setup 0x20000000 2048 "SEGGER RTT"
rtt start

# Re-export up/down channel 0 as a TCP server on port 9090
rtt server start 9090 0

# Optional tuning
rtt polling_interval 20        # ms between buffer polls (default 100)
rtt channels                   # list discovered channels

# Bidirectional: your terminal sees up-channel 0, typing goes to down-channel 0
nc localhost 9090

# Or drive it from a GDB/Tcl session:  monitor rtt start / monitor rtt channels

# Flash + run + live RTT terminal (chip name from `probe-rs chip list`)
probe-rs run --chip STM32L4R5ZITx target/thumbv7em-none-eabihf/release/app

# Attach to an already-running target WITHOUT reset/flash (preserve state)
probe-rs attach --chip STM32L4R5ZITx build/firmware.elf

# Run with:  cargo embed --release      (uses the [default] profile)
[default.general]
chip = "STM32L4R5ZITx"

[default.rtt]
enabled = true          # open the RTT terminal UI

[default.gdb]
enabled = false         # set true to also start a GDB server

# Terminal 1: open a J-Link session (SWD, our target). RTT auto-starts.
JLinkExe -device STM32L4R5ZI -if SWD -speed 4000 -autoconnect 1

# Terminal 2: text client to the RTT telnet server on 127.0.0.1:19021
JLinkRTTClient

# GUI alternative (multi-channel, logging to file):
JLinkRTTViewer