ARM Semihosting
printf via the Debugger

/* A generic semihosting call for Cortex-M.
 * r0 = operation number, r1 = pointer to arg block.
 * Returns the debugger's result value (also in r0). */
static inline int semihost(int op, void *arg_block)
{
    register int   r0 asm("r0") = op;          // operation -> r0
    register void *r1 asm("r1") = arg_block;    // arg pointer -> r1
    asm volatile(
        "bkpt #0xAB"        // the semihosting trap (0xBEAB)
        : "+r"(r0)          // r0 is read AND written (return value)
        : "r"(r1)           // r1 is an input
        : "memory");        // debugger may touch our RAM
    return r0;
}

# --- CPU / FPU: STM32L4R5 is Cortex-M4 with single-precision FPU ---
CPU     = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard

# --- Compile ---
CFLAGS  = $(CPU) -Og -g3 -Wall -ffunction-sections -fdata-sections

# --- Link: rdimon.specs routes newlib syscalls to semihosting ---
LDFLAGS = $(CPU) --specs=rdimon.specs -Wl,--gc-sections \
          -T STM32L4R5ZI_FLASH.ld \
          -Wl,--start-group -lc -lrdimon -Wl,--end-group \
          -Wl,-Map=firmware.map

#include <stdio.h>

/* Provided by librdimon. No header ships it, so declare it. */
extern void initialise_monitor_handles(void);

int main(void)
{
    initialise_monitor_handles();   // MUST run before the first printf

    printf("STM32L4R5 alive, HCLK bring-up OK\n");
    for (int i = 0; i < 3; i++)
        printf("tick %d\n", i);

    while (1) { }
}

# Option A: generic ST-LINK interface + STM32L4 target
openocd -f interface/stlink.cfg -f target/stm32l4x.cfg

# Option B: the ready-made Nucleo-L4 board file (does both)
openocd -f board/st_nucleo_l4.cfg

# OpenOCD now listens: GDB on :3333, telnet on :4444

target extended-remote localhost:3333
monitor reset halt
monitor arm semihosting enable
load
continue
# printf output now streams to the OpenOCD console window.

arm-none-eabi-gdb firmware.elf -x run.gdb

# or fully inline:
arm-none-eabi-gdb firmware.elf \
  -ex "target extended-remote localhost:3333" \
  -ex "monitor reset halt" \
  -ex "monitor arm semihosting enable" \
  -ex "load" \
  -ex "continue"

#include <stdio.h>
#include <stdint.h>

/* Supplied by librdimon (via --specs=rdimon.specs). */
extern void initialise_monitor_handles(void);

int main(void)
{
    /* SystemInit() / clock config from CubeMX has already run
       out of the reset handler before main(). */
    initialise_monitor_handles();

    printf("=== STM32L4R5 semihosting bring-up ===\n");
    printf("SCB CPUID @ 0xE000ED00 = 0x%08lX\n",
           *(volatile uint32_t *)0xE000ED00);   // should read 0x410FC241 (Cortex-M4 r0p1)

    for (uint32_t i = 0; i < 5; i++) {
        printf("loop %lu\n", i);
        for (volatile uint32_t d = 0; d < 200000; d++) { }  // crude delay
    }

    printf("done.\n");
    while (1) { }
}

PREFIX  = arm-none-eabi-
CC      = $(PREFIX)gcc
OBJCOPY = $(PREFIX)objcopy

CPU     = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard
CFLAGS  = $(CPU) -Og -g3 -Wall -ffunction-sections -fdata-sections \
          -DSTM32L4R5xx
LDFLAGS = $(CPU) --specs=rdimon.specs -Wl,--gc-sections \
          -T STM32L4R5ZI_FLASH.ld \
          -Wl,--start-group -lc -lrdimon -Wl,--end-group \
          -Wl,-Map=firmware.map

SRCS    = main.c system_stm32l4xx.c startup_stm32l4r5xx.s
OBJS    = $(addsuffix .o,$(basename $(SRCS)))

all: firmware.elf firmware.bin

%.o: %.c
	$(CC) $(CFLAGS) -c $< -o $@
%.o: %.s
	$(CC) $(CFLAGS) -c $< -o $@

firmware.elf: $(OBJS)
	$(CC) $(OBJS) $(LDFLAGS) -o $@
	$(PREFIX)size $@

firmware.bin: firmware.elf
	$(OBJCOPY) -O binary $< $@

clean:
	rm -f $(OBJS) firmware.elf firmware.bin firmware.map

# 1) Build
make

# 2) Terminal A — start the GDB server (leave it running)
openocd -f interface/stlink.cfg -f target/stm32l4x.cfg

# 3) Terminal B — connect, enable semihosting, flash, run
arm-none-eabi-gdb firmware.elf -x run.gdb

Info : halted: PC: 0x08000abc
Info : semihosting is enabled
=== STM32L4R5 semihosting bring-up ===
SCB CPUID @ 0xE000ED00 = 0x410FC241
loop 0
loop 1
loop 2
loop 3
loop 4
done.

#include <stdint.h>
#include <sys/stat.h>

/* Operation numbers from the ARM semihosting spec. */
#define SYS_WRITE0  0x04
#define SYS_WRITE   0x05
#define SYS_READC   0x07

/* The one-instruction primitive: r0=op, r1=args, ret in r0. */
static inline int semihost(int op, void *args)
{
    register int   r0 asm("r0") = op;
    register void *r1 asm("r1") = args;
    asm volatile("bkpt #0xAB"
                 : "+r"(r0) : "r"(r1) : "memory");
    return r0;
}

/* SYS_WRITE param block: { handle, data ptr, length }.
   Returns the number of bytes NOT written (0 == success). */
static int sh_write(int handle, const char *buf, int len)
{
    volatile uint32_t block[3] = { (uint32_t)handle,
                                   (uint32_t)buf,
                                   (uint32_t)len };
    return semihost(SYS_WRITE, (void *)block);
}

/* newlib calls _write() for every printf/putchar/fwrite(stdout).
   Handle 1 == stdout by convention. */
int _write(int fd, const char *buf, int len)
{
    (void)fd;                       // treat all fds as the console
    int not_written = sh_write(1, buf, len);
    return len - not_written;       // bytes actually written
}

/* Minimal stubs so the linker is happy with --specs=nano.specs. */
int _read(int fd, char *buf, int len)     { (void)fd;(void)buf;(void)len; return 0; }
int _close(int fd)                        { (void)fd; return -1; }
int _lseek(int fd, int off, int dir)      { (void)fd;(void)off;(void)dir; return 0; }
int _fstat(int fd, struct stat *st)       { (void)fd; st->st_mode = S_IFCHR; return 0; }
int _isatty(int fd)                       { (void)fd; return 1; }

static inline void sh_puts(const char *s)
{
    semihost(SYS_WRITE0, (void *)s);   // r1 -> NUL-terminated string
}

// ...anywhere in your code, even before clocks are configured:
sh_puts("reached HAL_Init\n");

#include <stdint.h>

/* DHCSR bit0 (C_DEBUGEN) is set only when a debugger has enabled
   halting-debug. Check it before issuing any semihosting trap so the
   same image can run both under the probe and standalone. */
static inline int debugger_attached(void)
{
    return (*(volatile uint32_t *)0xE000EDF0) & 0x1u;   // CoreDebug->DHCSR & C_DEBUGEN
}

void log_msg(const char *s)
{
    if (debugger_attached())
        sh_puts(s);        // safe: a probe is servicing traps
    // else: silently skip — no BKPT, no HardFault
}