probe-rs
Modern CLI Flash & Debug for STM32L4R5

# Recommended for Rust users — builds probe-rs, cargo-flash, cargo-embed
cargo install probe-rs-tools --locked

# Or prebuilt binaries (no Rust toolchain needed)
curl --proto '=https' --tlsv1.2 -LsSf \
  https://github.com/probe-rs/probe-rs/releases/latest/download/probe-rs-tools-installer.sh | sh

# Bleeding-edge (git) if you need a just-added target
cargo install probe-rs-tools --git https://github.com/probe-rs/probe-rs --locked

# Optional: shell completion
probe-rs complete install

# Install the maintained rules, then reload — no sudo needed afterwards
sudo curl -L \
  https://probe.rs/files/69-probe-rs.rules \
  -o /etc/udev/rules.d/69-probe-rs.rules
sudo udevadm control --reload-rules
sudo udevadm trigger
# Re-plug the probe (or add yourself to the plugdev group) after this.

# Enumerate connected debug probes
probe-rs list
# The following debug probes were found:
# [0]: STLink V3 -- 0483:374e:002700xxxxxx (ST-LINK)

# Interrogate the target itself (ARM DAP, cores, ROM tables)
probe-rs info --chip STM32L4R5ZITx
# If SWD is stuck (e.g. firmware reconfigures SWD pins), add:
probe-rs info --chip STM32L4R5ZITx --connect-under-reset

# List every matching variant probe-rs knows
probe-rs chip list | grep -i STM32L4R5
# STM32L4R5AGxx / STM32L4R5AIxx / STM32L4R5QGxx / STM32L4R5QIxx
# STM32L4R5VGxx / STM32L4R5VIxx / STM32L4R5ZGxx / STM32L4R5ZITx ...

# Detailed memory map / flash algo for one variant
probe-rs chip info STM32L4R5ZITx

# Flash an ELF — format is auto-detected, addresses come from the ELF
probe-rs download --chip STM32L4R5ZITx firmware.elf

# Be explicit about the format when it is ambiguous
probe-rs download --chip STM32L4R5ZITx --binary-format elf firmware.elf

# Raw BIN has no addresses — you MUST give a base address
probe-rs download --chip STM32L4R5ZITx \
  --binary-format bin --base-address 0x08000000 firmware.bin

# Full chip erase before writing (vs. default page-by-page erase)
probe-rs download --chip STM32L4R5ZITx --chip-erase firmware.elf

# CI-friendly: no progress bars, and pick a specific probe
probe-rs download --chip STM32L4R5ZITx \
  --probe 0483:374e --disable-progressbars firmware.elf

# Compare flash against an ELF without reprogramming
probe-rs verify --chip STM32L4R5ZITx firmware.elf

# Erase the whole chip (guard flag required so you don't wipe by accident)
probe-rs erase --chip STM32L4R5ZITx --allow-erase-all

# Pulse a reset and let the target run
probe-rs reset --chip STM32L4R5ZITx

# Flash, reset, and attach RTT in one shot
probe-rs run --chip STM32L4R5ZITx \
  target/thumbv7em-none-eabihf/debug/my-firmware

# Halt + backtrace on panic!() and on a HardFault
probe-rs run --chip STM32L4R5ZITx \
  --catch-panic --catch-hardfault \
  target/thumbv7em-none-eabihf/debug/my-firmware

# Force a full RAM scan for the RTT control block (release/LTO builds)
probe-rs run --chip STM32L4R5ZITx \
  --rtt-scan-memory \
  --always-print-stacktrace \
  target/thumbv7em-none-eabihf/release/my-firmware

[target.thumbv7em-none-eabihf]
# cargo run == flash + reset + RTT/defmt for the L4R5
runner = "probe-rs run --chip STM32L4R5ZITx"
rustflags = [
  "-C", "link-arg=-Tlink.x",     # cortex-m-rt linker script
  "-C", "link-arg=-Tdefmt.x",    # defmt symbol table
]

[build]
target = "thumbv7em-none-eabihf"

[env]
DEFMT_LOG = "debug"            # host-side log-level filter

MEMORY
{
  FLASH : ORIGIN = 0x08000000, LENGTH = 2048K
  RAM   : ORIGIN = 0x20000000, LENGTH = 640K
}

[dependencies]
cortex-m      = "0.7"
cortex-m-rt   = "0.7"
defmt         = "0.3"
defmt-rtt     = "0.4"            # the RTT transport for defmt
panic-probe   = { version = "0.3", features = ["print-defmt"] }

#![no_std]
#![no_main]

use defmt_rtt as _;      // global defmt logger over RTT
use panic_probe as _;     // panic handler: log via defmt, then halt
use cortex_m_rt::entry;

#[entry]
fn main() -> ! {
    defmt::info!("STM32L4R5ZI booted, RTT is live");

    let mut n: u32 = 0;
    loop {
        defmt::debug!("heartbeat #{}", n);
        n = n.wrapping_add(1);
        cortex_m::asm::delay(4_000_000);

        if n == 5 {
            defmt::error!("simulated fault -> panic");
            panic!("boom at n={}", n); // --catch-panic halts here with a backtrace
        }
    }
}

# $ cargo run
      Erasing ✔ [00:00:00]  12.00 KiB/12.00 KiB
  Programming ✔ [00:00:00]  12.00 KiB/12.00 KiB
      Finished in 0.41s
INFO  STM32L4R5ZI booted, RTT is live
DEBUG heartbeat #0
DEBUG heartbeat #1
...
ERROR simulated fault -> panic
ERROR panicked at src/main.rs:22:13: boom at n=5
# stack backtrace, with source locations, printed by --catch-panic
   0: my_firmware::main
        at src/main.rs:22
   1: main
   ...

use rtt_target::{rtt_init_print, rprintln};

#[entry]
fn main() -> ! {
    rtt_init_print!();                 // installs the RTT control block
    rprintln!("hello over RTT channel 0");
    let mut i = 0;
    loop {
        rprintln!("counter = {}", i);
        i += 1;
        cortex_m::asm::delay(8_000_000);
    }
}

# Build (release) + flash + open the default profile
cargo embed --release

# Select a named profile defined in Embed.toml (positional arg)
cargo embed --release with_rtt

# cargo-embed is part of probe-rs-tools; also: cargo flash
cargo flash --chip STM32L4R5ZITx --release

[default.probe]
# Pin a specific probe when several are attached
# usb_vid = "0483"
# usb_pid = "374e"
# serial  = "002700xxxxxx"
protocol = "Swd"            # "Swd" or "Jtag"
# speed  = 4000              # link speed in kHz

[default.general]
chip = "STM32L4R5ZITx"    # the target — this is the key line
chip_descriptions = []
log_level = "WARN"
connect_under_reset = false  # true == assert NRST while attaching

[default.flashing]
enabled = true
restore_unwritten_bytes = false
do_chip_erase = false        # true == full erase instead of page-by-page

[default.reset]
enabled = true
halt_afterwards = false      # true == stay halted after reset (debug from reset)

[default.rtt]
enabled = true               # open the RTT UI after flashing
timeout = 3000               # ms to keep retrying the RTT attach
show_timestamps = true
log_enabled = false          # save RTT history to disk
log_path = "./logs"
# up_mode = "BlockIfFull"    # global default overflow mode
channels = [
  # up/down are channel numbers; format is required
  { up = 0, down = 0, name = "logs", up_mode = "NoBlockTrim", format = "Defmt" },
]

[default.gdb]
enabled = false
gdb_connection_string = "127.0.0.1:1337"

# Attach to the running target and stream RTT — no reset, no re-flash.
# Pass the same ELF so defmt frames and backtraces can be decoded.
probe-rs attach --chip STM32L4R5ZITx \
  target/thumbv7em-none-eabihf/debug/my-firmware

# Reconnect over a flaky SWD line by asserting reset first
probe-rs attach --chip STM32L4R5ZITx --connect-under-reset my-firmware

# Terminal 1: open a GDB server on the default 127.0.0.1:1337
probe-rs gdb --chip STM32L4R5ZITx

# Terminal 2: connect a GDB and load symbols
arm-none-eabi-gdb target/thumbv7em-none-eabihf/debug/my-firmware
# (gdb) target remote :1337
# (gdb) load
# (gdb) break main
# (gdb) continue

{
  "version": "0.2.0",
  "configurations": [
    {
      "type": "probe-rs-debug",
      "request": "launch",
      "name": "L4R5 (probe-rs)",
      "chip": "STM32L4R5ZITx",
      "coreConfigs": [
        {
          "programBinary": "target/thumbv7em-none-eabihf/debug/my-firmware",
          "rttEnabled": true
        }
      ]
    }
  ]
}