Vivado & Quartus
IP Tasarımı & Bitstream

# Yeni Block Design oluştur
create_bd_design "design_1"

# Zynq PS IP ekle
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 ps7_0

# ZedBoard preset uygula
set_property -dict [list \
  CONFIG.PCW_USE_S_AXI_HP0 {1} \
  CONFIG.PCW_USE_M_AXI_GP0 {1} \
  CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
  CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
  CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
  CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
] [get_bd_cells ps7_0]

# PS saatini PL'e bağla
connect_bd_net [get_bd_pins ps7_0/FCLK_CLK0] \
               [get_bd_pins ps7_0/M_AXI_GP0_ACLK]

-- Şablona eklenen özel register mantığı
-- REG0 (0x00): kontrol register'ı
-- REG1 (0x04): veri çıkışı
-- REG2 (0x08): durum (salt okunur)
-- REG3 (0x0C): kesme enable

-- Yazma işlemi (şablonun write bölümüne ekle)
when b"00" =>
    for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
        if ( S_AXI_WSTRB(byte_index) = '1' ) then
            slv_reg0(byte_index*8+7 downto byte_index*8) <=
                S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
        end if;
    end loop;

-- Uygulama mantığı (entity port'larına bağla)
CTRL_OUT  <= slv_reg0(7 downto 0);   -- kontrol bitleri
DATA_OUT  <= slv_reg1;                 -- veri çıkışı
slv_reg2  <= "000" & STATUS_IN;       -- durum okuma
IRQ_EN    <= slv_reg3(0);             -- kesme etkinleştir

// AXI4-Lite yazma FSM (basitleştirilmiş)
always @(posedge S_AXI_ACLK) begin
    if (!S_AXI_ARESETN) begin
        reg_ctrl <= 32'h0;
        reg_data <= 32'h0;
        reg_irqen <= 32'h0;
    end else if (slv_reg_wren) begin
        case (axi_awaddr[3:2])
            2'h0: reg_ctrl  <= S_AXI_WDATA;
            2'h1: reg_data  <= S_AXI_WDATA;
            // 2'h2: STATUS salt okunur — yazma yok
            2'h3: reg_irqen <= S_AXI_WDATA;
        endcase
    end
end

// Okuma multiplexer
always @(*) begin
    case (axi_araddr[3:2])
        2'h0: reg_data_out = reg_ctrl;
        2'h1: reg_data_out = reg_data;
        2'h2: reg_data_out = {{31}}{1'b0}, status_in};
        2'h3: reg_data_out = reg_irqen;
    endcase
end

module axis_pass_filter #(
    parameter DATA_WIDTH = 32
)(
    input  wire                   aclk,
    input  wire                   aresetn,
    // Slave (giriş)
    input  wire [DATA_WIDTH-1:0]  s_tdata,
    input  wire                   s_tvalid,
    output wire                   s_tready,
    input  wire                   s_tlast,
    // Master (çıkış)
    output wire [DATA_WIDTH-1:0]  m_tdata,
    output wire                   m_tvalid,
    input  wire                   m_tready,
    output wire                   m_tlast,
    // Kontrol (AXI-Lite'dan)
    input  wire [DATA_WIDTH-1:0]  threshold
);
    // Eşiği geçen örnekleri maskele
    wire pass = (s_tdata <= threshold);
    assign m_tdata  = pass ? s_tdata : {DATA_WIDTH{1'b0}};
    assign m_tvalid = s_tvalid;
    assign s_tready = m_tready;
    assign m_tlast  = s_tlast;
endmodule

## Birincil saat — 100 MHz PS FCLK0
create_clock -period 10.000 -name clk_100 \
    [get_ports {FCLK_CLK0}]

## ZedBoard — harici 100 MHz osilatör (PL direkt)
create_clock -period 10.000 -name sys_clk \
    [get_ports {sys_clk_p}]

## I/O zamanlama (AXI master/slave dışı GPIO)
set_input_delay  -clock clk_100 2.0 [get_ports {btn_*}]
set_output_delay -clock clk_100 2.0 [get_ports {led_*}]

## Yanlış yol (false path) — asenkron reset
set_false_path -from [get_ports {cpu_resetn}]

## CDC — farklı saat etki alanları arası yol
set_false_path -from [get_clocks clk_100] \
               -to   [get_clocks clk_200]

// Zynq-7000 BOOT.BIN yapılandırması
the_ROM_image:
{
    [bootloader] fsbl.elf        // FSBL — OCM'de çalışır
    design_1_wrapper.bit         // PL bitstream
    u-boot.elf                   // U-Boot
}

# Vitis veya Petalinux araçlarıyla
bootgen -arch zynq -image boot.bif -w on -o BOOT.BIN

# SD karta kopyala
cp BOOT.BIN /media/boot/
cp image.ub /media/boot/   # FIT imaj (kernel + DTB + initrd)

# veya TFTP ile U-Boot'tan yükle
# U-Boot prompt:
# tftpboot 0x3000000 image.ub && bootm 0x3000000

// Cyclone V SoC — sysmgr üzerinden köprü kontrolü
// Kernel sürücüsü: drivers/fpga/altera-hps2fpga.c

// Kullanıcı alanından sysfs üzerinden:
// echo 1 > /sys/bus/platform/drivers/altera-hps2fpga/ff400000.bridge/enable

// veya devmem2 aracıyla SYSMGR.FPGAINTF register'ı:
// SYSMGR_BASE = 0xFFD08000
// FPGAINTF_EN_2 offset = 0x28
// bit[0]: H2F, bit[1]: LWH2F, bit[2]: F2H

#define SYSMGR_BASE    0xFFD08000UL
#define FPGAINTF_EN_2  0x28

volatile uint32_t *sysmgr = mmap_region(SYSMGR_BASE, 0x1000);
sysmgr[FPGAINTF_EN_2 / 4] |= (1 << 0) | (1 << 1);  // H2F + LWH2F

module pwm_core (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        enable,
    input  wire        polarity,
    input  wire [31:0] period,    // saat döngüsü sayısı - 1
    input  wire [31:0] duty,      // yüksek süre
    output reg         pwm_out,
    output wire        running
);
    reg [31:0] counter = 0;

    assign running = enable;

    always @(posedge clk) begin
        if (!rst_n || !enable) begin
            counter <= 0;
            pwm_out <= polarity ? 1'b0 : 1'b1;
        end else begin
            if (counter >= period)
                counter <= 0;
            else
                counter <= counter + 1;

            if (counter < duty)
                pwm_out <= polarity ? 1'b1 : 1'b0;
            else
                pwm_out <= polarity ? 1'b0 : 1'b1;
        end
    end
endmodule

#include <stdio.h>
#include <stdint.h>
#include <fcntl.h>
#include <sys/mman.h>

#define PWM_BASE   0x40000000UL
#define MAP_SIZE   0x10000UL

#define REG_CTRL   0x00
#define REG_PERIOD 0x04
#define REG_DUTY   0x08
#define REG_STATUS 0x0C

/* 100 MHz saat, 10 kHz PWM, %75 görev döngüsü */
#define CLK_HZ     100000000UL
#define PWM_HZ     10000UL
#define DUTY_PCT   75

int main(void)
{
    uint32_t period = CLK_HZ / PWM_HZ - 1;         // 9999
    uint32_t duty   = period * DUTY_PCT / 100;      // 7499

    int fd = open("/dev/mem", O_RDWR | O_SYNC);
    volatile uint32_t *pwm =
        mmap(NULL, MAP_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, PWM_BASE);

    pwm[REG_CTRL   / 4] = 0;       /* durdur */
    pwm[REG_PERIOD / 4] = period;
    pwm[REG_DUTY   / 4] = duty;
    pwm[REG_CTRL   / 4] = 1;       /* enable, normal polarity */

    printf("PWM: %u Hz, duty=%u/%u (%d%%)\n",
           (uint32_t)PWM_HZ, duty, period, DUTY_PCT);
    printf("STATUS: 0x%08X\n", pwm[REG_STATUS / 4]);

    munmap((void *)pwm, MAP_SIZE);
    close(fd);
    return 0;
}